XR16C854IV-F Exar Corporation, XR16C854IV-F Datasheet - Page 21
![IC UART FIFO 128B QUAD 64LQFP](/photos/29/6/290652/lqfp64_sml.jpg)
XR16C854IV-F
Manufacturer Part Number
XR16C854IV-F
Description
IC UART FIFO 128B QUAD 64LQFP
Manufacturer
Exar Corporation
Type
Quad UART with 128-byte FIFOsr
Datasheet
1.XR16C854IV-F.pdf
(54 pages)
Specifications of XR16C854IV-F
Number Of Channels
4, QUART
Package / Case
64-LQFP
Features
*
Fifo's
128 Byte
Protocol
RS232, RS485
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
2 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
3 mA to 6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.97 V to 5.5 V
No. Of Channels
4
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1276
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16C854IV-F
Manufacturer:
HYNIX
Quantity:
101
Company:
Part Number:
XR16C854IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
xr
REV. 3.0.1
The 854 resumes normal operation by any of the following:
If the 854 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the 854 is awakened by the modem inputs, a read
to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an
interrupt is pending in any channel. The 854 will stay in the sleep mode of operation until it is disabled by
setting IER bit-4 to a logic 0.
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, CSC#, CSD# and modem input lines remain
steady when the 854 is in sleep mode, the maximum current will be in the microamp range as specified in the
DC Electrical Characteristics on
mode, the current can be up to 100 times more. If any of those signals are toggling or floating, then an external
buffer would be required to keep the address, data and control lines steady to achieve the low current.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. Also, make sure the RX input is idling at logic 1 or “marking” condition
during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or another
type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the system design
engineer can use a 47k ohm pull-up resistor on the RX A-D inputs.
The 854 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
2.20
■
■
■
a receive data start bit transition (logic 1 to 0)
a data byte is loaded to the transmitter, THR or FIFO
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
Internal Loopback
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
page
41. If the input lines are floating or are toggling while the 854 is in sleep
21
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
XR16C854/854D