XR16C854IV-F Exar Corporation, XR16C854IV-F Datasheet - Page 5
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XR16C854IV-F
Manufacturer Part Number
XR16C854IV-F
Description
IC UART FIFO 128B QUAD 64LQFP
Manufacturer
Exar Corporation
Type
Quad UART with 128-byte FIFOsr
Datasheet
1.XR16C854IV-F.pdf
(54 pages)
Specifications of XR16C854IV-F
Number Of Channels
4, QUART
Package / Case
64-LQFP
Features
*
Fifo's
128 Byte
Protocol
RS232, RS485
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
2 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
3 mA to 6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.97 V to 5.5 V
No. Of Channels
4
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1276
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16C854IV-F
Manufacturer:
HYNIX
Quantity:
101
Company:
Part Number:
XR16C854IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Pin Description
xr
REV. 3.0.1
RXRDYC#
RXRDYD#
TXRDYB#
TXRDYC#
TXRDYD#
RXRDYA#
RXRDYB#
TXRDYA#
INTSEL
(IRQ#)
CSD#
(N.C.)
(N.C.)
N
INTC
INTD
INTA
INTB
AME
64-LQFP
P
42
12
37
43
IN
6
-
-
-
-
-
-
-
-
-
#
68-PLCC
P
54
15
21
49
55
65
IN
-
-
-
-
-
-
-
-
#
100-QFP
P
100
68
12
18
63
69
87
25
56
81
31
50
82
IN
5
#
T
(OD)
YPE
O
O
O
O
I
I
UART channels A-D Transmitter Ready (active low). The outputs
provide the TX FIFO/THR status for transmit channels A-D. See
Table
When 16/68# pin is at logic 1, this input is chip select D (active low)
to enable channel D in the device.
When 16/68# pin is at logic 0, this input is not used.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is at logic 1 for Intel bus interface, this ouput
becomes channel A interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTA is set to
the active mode when MCR[3] is set to a logic 1. INTA is set to the
three state mode when MCR[3] is set to a logic 0 (default). See
MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is at logic 1 for Intel bus interface, these ouputs
become the interrupt outputs for channels B, C, and D. The output
state is defined by the user through the software setting of MCR[3].
The interrupt outputs are set to the active mode when MCR[3] is
set to a logic 1 and are set to the three state mode when MCR[3] is
set to a logic 0 (default). See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, these out-
puts are unused and will stay at logic zero level. Leave these out-
puts unconnected.
Motorola bus interface is not available on the 64 pin package.
Interrupt Select (active high, input with internal pull-down).
When 16/68# pin is at logic 1 for Intel bus interface, this pin can be
used in conjunction with MCR bit-3 to enable or disable the INT A-
D pins or override MCR bit-3 and enable the interrupt outputs.
Interrupt outputs are enabled continuously by making this pin a
logic 1. Making this pin a logic 0 allows MCR bit-3 to enable and
disable the interrupt output pins. In this mode, MCR bit-3 is set to
a logic 1 to enable the continuous output. See MCR bit-3 descrip-
tion for full detail. This pin must be at logic 0 in the Motorola bus
interface mode. Due to pin limitations on 64 pin packages, this pin
is not available. To cover this limitation, two 64 pin LQFP pack-
ages versions are offered. The XR16C854D operates in the con-
tinuous interrupt enable mode by bonding this pin to VCC
internally.
UART channels A-D Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channels A-D. See
Table
5
5. If these outputs are unused, leave them unconnected.
5. If these outputs are unused, leave them unconnected.
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
D
ESCRIPTION
XR16C854/854D