XR17D158CV-F Exar Corporation, XR17D158CV-F Datasheet - Page 29

• Manufacturer Part Number: XR17D158CV-F
• Description: IC UART PCI BUS OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR17D158CV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1291

xr
REV. 1.2.2
The THR and RHR register address for channel 0 to channel 7 is shown in
for each channel 0 to 7 are located sequentially at address 0x0000, 0x0200, 0x0400, 0x0600, 0x0800,
0x0A000, 0x0C00 and 0x0E00. Transmit data byte is loaded to the THR when writing to that address and
receive data is unloaded from the RHR register when reading that address. Both THR and RHR registers are
16C550 compatible in 8-bit format, so each bus operation can only write or read in bytes.
4.2
Data Bit-31
PCI Bus
B7 B6 B5 B4 B3 B2 B1 B0
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT.
Transmit Data Byte n+3
T
ABLE
CH0 0x000 Read RHR
CH2 0x400 Read RHR
CH3 0x600 Read RHR
CH4 0x800 Read RHR
CH3 0x600 Write THR
CH5 0xA00 Write THR
CH0 0x000 Write THR
CH1 0x200 Write THR
CH1 0x200 Read RHR
CH2 0x400 Write THR
CH4 0x800 Write THR
CH5 0xA00 Read RHR
CH6 0xC00 Read RHR
CH7 0xE00 Read RHR
9: T
CH6 0xC00 Write THR
CH7 0xE00 Write THR
Channel 0 to 7 Transmit Data in 32-bit alignment through the Configuration Register Address
RANSMIT AND
THR and RHR Address Locations For CH0 to CH7 (16C550 Compatible)
0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00
B7 B6 B5 B4 B3 B2 B1 B0
Transmit Data Byte n+2
R
ECEIVE
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
D
ATA
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
R
EGISTER IN
29
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
B7 B6 B5 B4 B3 B2 B1 B0
Transmit Data Byte n+1
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
B
YTE FORMAT
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Table 9
, 16C550
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
B7 B6 B5 B4 B3 B2 B1 B0
below. The THR and RHR
Transmit Data Byte n+0
COMPATIBLE
THRRHR1
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
XR17D158
Data Bit-0
PCI Bus