XR17D158CV-F Exar Corporation, XR17D158CV-F Datasheet - Page 42

• Manufacturer Part Number: XR17D158CV-F
• Description: IC UART PCI BUS OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR17D158CV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1291

XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
IER[4]: Reserved
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
IER[6]: RTS#/DTR# Output Interrupt Enable (requires EFR bit-4=1)
The RTS# or DTR# output is selected via MCR bit-2. See
• Logic 0 = Disable the RTS#/DTR# interrupt (default).
• Logic 1 = Enable the RTS#/DTR# interrupt. The UART issues an interrupt when the RTS#/DTR# pin makes
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
The CTS# or DSR# input is selected via MCR bit-2. See
• Logic 0 = Disable the CTS#/DSR# interrupt (default).
• Logic 1 = Enable the CTS#/DSR# interrupt. The UART issues an interrupt when CTS# pin makes a transi-
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Inter-
rupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR
will give the user the current highest pending interrupt level to be serviced with others queued up for next ser-
vice. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table,
Table
ated with each of these interrupt levels.
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by the a 4-char plus 12 bits delay timer if the RX FIFO level is less than the RX trigger
• TXRDY is by LSR bit-5 (or bit-6 in auto RS485 control).
• MSR is by any of the MSR bits, 0, 1, 2 and 3.
• Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
• CTS#/DSR# is by a change of state on the input pin (from LOW to HIGH) with auto flow control enabled,
• RTS#/DTR# is when its receiver changes the state of the output pin (from LOW to HIGH) during auto RTS/
• Wake-up Indicator: when the UART comes out of sleep mode.
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
• TXRDY interrupt is cleared by a read to the ISR register.
• MSR interrupt is cleared by a read to the MSR register.
• Xon or Xoff character interrupt is cleared by a read to ISR register.
• Special character interrupt is cleared by a read to ISR register or after the next character is received.
• RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
• Wake-up Indicator is cleared by a read to the INT0 register.
5.8.5
details.
a transition.
tion.
level.
EFR bit-7, and depending on selection of MCR bit-2.
DTR flow control enabled by EFR bit-6 and selection of MCR bit-2.
14, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associ-
Interrupt Status Register (ISR) - Read-Only
42
Table 11
Table 11
or MCR[2] for complete details.
or MCR[2] for complete details.
xr
REV. 1.2.2