XR16L2750IM-F Exar Corporation, XR16L2750IM-F Datasheet - Page 24
![IC UART FIFO 64B DUAL 48TQFP](/photos/16/10/161019/tqfp-48_sml.jpg)
XR16L2750IM-F
Manufacturer Part Number
XR16L2750IM-F
Description
IC UART FIFO 64B DUAL 48TQFP
Manufacturer
Exar Corporation
Type
IrDA or RS- 485r
Datasheet
1.XR16L2750CM-F.pdf
(48 pages)
Specifications of XR16L2750IM-F
Number Of Channels
2, DUART
Package / Case
48-TQFP
Features
*
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.25 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
6.25 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
5 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
No. Of Channels
2
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.25V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
TQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1280
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16L2750IM-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR16L2750IM-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
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IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
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IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
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The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
associated with each of these interrupt levels.
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4.4
4.4.1
4.4.2
Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.
RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Interrupt Status Register (ISR) - Read-Only
Interrupt Generation:
Interrupt Clearing:
Table
9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
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REV. 1.2.1