XR16L2750IM-F Exar Corporation, XR16L2750IM-F Datasheet - Page 35
![IC UART FIFO 64B DUAL 48TQFP](/photos/16/10/161019/tqfp-48_sml.jpg)
XR16L2750IM-F
Manufacturer Part Number
XR16L2750IM-F
Description
IC UART FIFO 64B DUAL 48TQFP
Manufacturer
Exar Corporation
Type
IrDA or RS- 485r
Datasheet
1.XR16L2750CM-F.pdf
(48 pages)
Specifications of XR16L2750IM-F
Number Of Channels
2, DUART
Package / Case
48-TQFP
Features
*
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.25 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
6.25 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
5 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
No. Of Channels
2
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.25V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
TQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1280
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16L2750IM-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR16L2750IM-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
xr
REV. 1.2.1
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be
modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This
feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
•
•
EFR[5]: Special Character Detect Enable
•
•
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the next upper trigger level or hysteresis level. RTS# will return LOW when FIFO data
falls below the next lower trigger level. The RTS# output must be asserted (LOW) before the auto RTS can
take effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.
•
•
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•
•
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see
4.19.1
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW.
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
Table
6.
35
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
XR16L2750