STEVAL-PCC012V1 STMicroelectronics, STEVAL-PCC012V1 Datasheet - Page 54

• Manufacturer Part Number: STEVAL-PCC012V1
• Description: BOARD DEM CONN GATEWAY STM32F107
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: Other Power Managementr

Specifications of STEVAL-PCC012V1

• Main Purpose: Interface, Connectivity
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: STM32F107
• Primary Attributes: Ethernet and 4 Digital/Analog Connectors
• Secondary Attributes: On-Board LEDs and Joystick
• Interface Type: Ethernet, USB, I2C, SPI, UART
• Operating Supply Voltage: 3.3 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: STM32F107xx
• Other names: 497-10757

Electrical characteristics
5.3.12
Table 35.
1. FT = 5V tolerant. To sustain a voltage higher than V
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
54/101
Symbol
V
R
R
C
V
V
I
MOS/NMOS contribution
lkg
hys
PU
PD
IH
IO
IL
Standard I/O input low level voltage
I/O FT
Standard I/O input high level voltage
I/O FT
Standard IO Schmitt trigger voltage
hysteresis
IO FT Schmitt trigger voltage hysteresis
Input leakage current
Weak pull-up
equivalent resistor
Weak pull-down
equivalent resistor
I/O pin capacitance
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
I/O static characteristics
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in
in
(1)
(1)
Figure 20
input low level voltage
input high level voltage
(2)
to the series resistance is minimum
Parameter
and
(5)
(5)
(4)
All pins except for
PA10
PA10
All pins except for
PA10
PA10
Figure 21
for 5 V tolerant I/Os.
Doc ID 15274 Rev 5
DD
(2)
+0.5 the internal pull-up/pull-down resistors must be disabled.
(~10% order)
V
V
Standard I/Os
SS
IN
Conditions
V
V
= 5 V,

IN
IN
V
Figure 18


IN
V
V
.
I/O FT
Table

SS
DD
V
DD
Table 35
9. All I/Os are CMOS and TTL
0.41 (V
0.42 (V
and
5% V
+1.3
–0.5
–0.5
Min
200
Figure 19
+1
30
30
8
8
STM32F105xx, STM32F107xx
DD
DD
DD
are derived from tests
(3)
–2)
–2)
Typ
40
11
40
11
5
for standard I/Os, and
0.28 (V
0.32 (V
V
+0.75
DD
Max
+0.8
5.5
1
50
15
50
15
3
+0.5
DD
DD
–2)
–2)
Unit
mV
mV
µA
k
k
pF
V