STEVAL-PCC012V1 STMicroelectronics, STEVAL-PCC012V1 Datasheet - Page 63

• Manufacturer Part Number: STEVAL-PCC012V1
• Description: BOARD DEM CONN GATEWAY STM32F107
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: Other Power Managementr

Specifications of STEVAL-PCC012V1

• Main Purpose: Interface, Connectivity
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: STM32F107
• Primary Attributes: Ethernet and 4 Digital/Analog Connectors
• Secondary Attributes: On-Board LEDs and Joystick
• Interface Type: Ethernet, USB, I2C, SPI, UART
• Operating Supply Voltage: 3.3 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: STM32F107xx
• Other names: 497-10757

STM32F105xx, STM32F107xx
I
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature, f
supply voltage conditions summarized in
Refer to
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
Table 42.
2
DuCy(SCK)
S - SPI interface characteristics
1/t
Symbol
t
t
t
w(SCKH)
t
w(SCKL)
t
t
su(NSS)
t
t
t
t
t
t
h(NSS)
t
r(SCK)
f(SCK)
t
f
su(MI)
t
v(MO)
h(MO)
su(SI)
a(SO)
v(SO)
h(SO)
h(MI)
c(SCK)
h(SI)
SCK
Section 5.3.12: I/O port characteristics
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access
time
Data output valid time Slave mode (after enable edge)
Data output valid time Master mode (after enable edge)
Data output hold time
Parameter
Doc ID 15274 Rev 5
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode (after enable edge)
Master mode (after enable edge)
Table
Conditions
9.
for more details on the input/output alternate
PCLK
PCLK
= 20 MHz
Table 42
= 36 MHz,
for SPI or in
Electrical characteristics
PCLKx
4 t
2 t
Min
30
32
10
PCLK
PCLK
50
4
5
5
5
frequency and V
Table 43
3*t
Max
18
70
60
34
2
18
PCLK
8
8
S).
for I
63/101
MHz
Unit
ns
ns
%
2
S
DD