SX1441EVK Semtech, SX1441EVK Datasheet - Page 33

• Manufacturer Part Number: SX1441EVK
• Description: KIT DEV FOR SX1441
• Manufacturer: Semtech
• Series: EasyBlue™r
• Type: Bluetoothr

Specifications of SX1441EVK

• For Use With/related Products: SX1441
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Other names: SX1441DVK; SX1441DVK

Personal Area Network
3.8.3 Block Diagram
Figure 15 shows the block diagram of the port PA.
3.8.4 Debounce Mode
Each bit of the port PA can be individually debounced by setting the corresponding bit in RegPADebounce. After
reset, the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted
only if eight consecutive samples are identical. Selection of the clock is done by the bit DebounceSelect in register
RegPACtrl.
3.8.5 Pull-ups/Snap-to-rail
Different functions are possible depending on the value of the registers RegPAPullup and RegPASnapToRail.
When the corresponding bit in RegPAPullup is cleared, the inputs are floating (pull-up and pull-down resistors are
disconnected). When the corresponding bits are set in RegPAPullup is 1 and cleared in RegPASnapToRail , a
pull-up resistor is connected to the input pin. Alternatively, when the corresponding bits are cleared in
RegPAPullup and set in RegPASnapToRail, the snap-to-rail function is active.
The snap-to-rail function connects a pull-up or pull-down resistor to the input pin depending on the value last forced
on the input pin. This function can be used for instance when the input port is connected to a tri-state bus. When
the bus is floating, the pull-up or pull-down maintains the bus in the last low impedance state before it became
floating until another low impedance output drives the bus. It also reduces the power consumption with respect to a
classic pull-up since it selects the pull-up or pull-down resistor that matches the detected input state.
The state of input pin is summarized in Table 50.
© Semtech 2006
DebounceSelect
0
1
VDDIO_DIG
Vss
logic
8
8
Table 49 - Debouncer clock selection
8
1
0
8x
Figure 15 - Structure of PA[7:0]
debounce
1
Port A
Debounce filter clock
slow (ck1kHz low prescaler output)
Fast (ck32kHz low prescaler output)
11
10
01
00
0
8x
DebFast
(RegPACtrl(0))
33
0
1
8
8
1
0
8x
8
8
8
8
RegPASnapToRail
RegPADebounce
RegPAPullup
RegPAEdge
RegPARes1
RegPARes0
RegPACtrl
RegPAIn
resetfromporta
SX1441 – Bluetooth® 1.2 SoC
Slow (1kHz)
Fast (32kHz)
interrupts
events
cntclocks
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Data Sheet