SX1441EVK Semtech, SX1441EVK Datasheet - Page 66

• Manufacturer Part Number: SX1441EVK
• Description: KIT DEV FOR SX1441
• Manufacturer: Semtech
• Series: EasyBlue™r
• Type: Bluetoothr

Specifications of SX1441EVK

• For Use With/related Products: SX1441
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Other names: SX1441DVK; SX1441DVK

Personal Area Network
3.14.3 Block Diagram
The microphone input is fully differential. The signal from the microphone between inputs VMIC_P and VMIC_N is
first amplified by a variable gain amplifier. The amplified signal is then sampled and digitized by the Σ-∆ ADC. The
single bit output stream from the ADC is then converted into 16-bit, 8 kHz, linear PCM data representing the audio
samples. These samples are sent to the PCM interface (connected to the Bluetooth Sequencer) or to the host
processor memory through the DMA interface depending on the settings of the RegCodecDataFlow configuration
register. The samples out of the ADC can also be directly read from the RegADCSampleH/-L registers.
The 16-bit digital data from either the Bluetooth Sequencer or the host processor memory through the DMA are
converted into a PWM bit stream by the DAC. The host processor can also write samples directly into the
RegDACSampleH/-L registers. This PWM bit stream is then amplified by the output power amplifier. The signal is
available between the PA_OUTP and PA_OUTN outputs. The output power amplifier is a class D amplifier. It
requires only a simple output filter. It is capable of driving a speaker directly if its impedance is equal or greater
than 32Ω.
The Codec also includes a Direct Memory Access to the host processor data memory (0x2000 to 0x3FEF) to read
and write 16-bit audio samples, defined as the read channel and the write channel. The area of the host processor
data memory used the write channel is defined by the two 16-bit pointers stored in RegDmaWrStartAddrH/-L and
RegDmaWrStopAddrH/-L. Similarly, the area of the host processor data memory used the read channel is defined
by the two 16-bit pointers stored in RegDmaRdStartAddrH/-L and RegDmaRdStopAddrH/-L. Software
engineering should make sure these two areas do not overlap with other application data otherwise this may lead
to unpredictable behavior.
The use of the DMA strictly requires the host processor clock is the same as the Codec input clock which is
SYS_CLOCK_IN (see 3.5.9).
To enable the read and/or write channels, the corresponding start and stop addresses must loaded into the internal
address pointers from the corresponding RegDma(Read/Write)(Start/Stop)(H/L) registers and the read and/or write
channel must be enabled. This is performed by setting appropriately the RegDmaCtrl register. These pointers are
then automatically incremented at the sampling frequency defined for the audio samples, to read and/or write one
samples after the other from/to the data memory.
When the DMA read or write pointer reach the value defined in RegDmaRdStopAddrH/-L or
RegDmaWrStopAddrH/-L an interrupt to the host processor is generated. The interrupt service routine must stop
the DMA access, write new start and stop addresses in RegDmaRdStartAddrH/-L and RegDmaRdStopAddrH/-
L, or RegDmaWrStartAddrH/-L and RegDmaWrStopAddrH/-L, and enable again the read or write channel. If
© Semtech 2006
VMIC_P
VMIC_N
PA_OUTP
PA_OUTN
references
Timing
preamplifier
Power
amplifier
references
Current &
voltage
CoolRISC data bus
Figure 29 - Codec block diagram
ADC
DAC
Configuration
66
registers
DMA
SX1441 – Bluetooth® 1.2 SoC
PCM
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Bluetooth
Sequencer
Data Sheet