SX1441EVK Semtech, SX1441EVK Datasheet - Page 73

• Manufacturer Part Number: SX1441EVK
• Description: KIT DEV FOR SX1441
• Manufacturer: Semtech
• Series: EasyBlue™r
• Type: Bluetoothr

Specifications of SX1441EVK

• For Use With/related Products: SX1441
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Other names: SX1441DVK; SX1441DVK

Personal Area Network
3.15.4 Configuration
The debug interface has 2 modes, GPIO mode (default) and Debug mode.
3.15.4.1
To enter GPIO mode the MSB bit of RegDbgMode register has to be set to 0. The default value after reset is low
(0).
The direction of each bit within DBG[7:0] (input only or input/output) can be individually set using the RegDbgDir
register. If RegDbgDir[i] = 1, both the input and output buffers are active on the corresponding pin. If
RegDbgDir[i] is 0, the corresponding DBG pin is an input only and the output buffer is in high impedance. After
reset DBG is in input only mode; RegDbgDir[i] is reset to 0.
The input values of DBG are available in RegDbgIn (read only). Reading is always direct - there is no debounce
function. In case of possible noise on input signals, a software debouncer with polling or an external hardware filter
has to be implemented. The input buffer is also active when the port is defined as output and allows reading back
of the effective value on the pin.
Data stored in RegDbgOut are output at DBG if RegDbgDir[i] is 1. The default value after reset is low (0).
3.15.4.2
To enter Debug mode the MSB bit of RegDbgMode register has to be set to 1.
© Semtech 2006
GPIO Mode
Debug Mode
D_OUT / CLK /
Sequencer
Sequencer
Bluetooth
Bluetooth
D_IN
FSYNC
Figure 36 – Codec Debug Interface block schematics
RegDbgDir
PCM_D_OUT / PCM_CLK / PCM_FSYNC
PCM_D_IN
RegDbgDir
0
1
RegDbgDir
73
0
1
RegDbgDir
D_OUT
D_IN / CLK /
FSYNC
SX1441 – Bluetooth® 1.2 SoC
CODEC
CODEC
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