SX1441EVK Semtech, SX1441EVK Datasheet - Page 39

• Manufacturer Part Number: SX1441EVK
• Description: KIT DEV FOR SX1441
• Manufacturer: Semtech
• Series: EasyBlue™r
• Type: Bluetoothr

Specifications of SX1441EVK

• For Use With/related Products: SX1441
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Other names: SX1441DVK; SX1441DVK

Personal Area Network
(1)
(2)
3.10.3 General Operation Overview
Counter A and Counter B are 8-bit counters which can be cascaded to form 16-bit counters. Counter C and
Counter D have the same features. The counters can also be used to generate two PWM outputs on PB[0] and
PB[1]. PWM signals can be generated with 8-, 10-, 12-, 14- or 16-bit precision.
Counters A and B can be captured by events on an internal or an external signal. The capture can be performed on
both 8-bit counters running individually on two different clock sources or on both cascaded counters to form a 16-
bit counter. In any case, the same capture signal is used for both counters. When the counters A and B are not
cascaded, they can be used in several configurations: A and B as counters, A and B as captured counters, A as
PWM and B as counter, A as PWM and B as captured counter. When counters C and D are not cascaded, both
can be used either as counters or counter C as PWM and counter D as counter.
Counters are enabled by RegCntOn. When counters are cascaded, the bit CntBEnable controls the counter A +
B, and CntDEnable controls the counter C + D.
© Semtech 2006
Pos
2
1
0
Pos
7:6
5:4
3:2
1:0
Pos
7
6
5
4
3
2
1
0
When writing to RegCntA or RegCntB, the processor writes the counter comparison values. When reading these
locations, the processor reads back either the actual counter value or the last captured value if the capture mode is
active.
When writing RegCntC or RegCntD, the processor writes the counter comparison values. When reading these locations,
the processor reads back the actual counter value.
RegCntConfig1
CascadeAB
CntPWM1
CntPWM0
RegCntConfig2
CapSel
CaptFunc
Pwm1Size
Pwm0Size
RegCntOn
CntDExtDiv
CntCExtDiv
CntBExtDiv
CntAExtDiv
CntDEnable
CntCEnable
CntBEnable
CntAEnable
r/w
rw
rw
rw
r/w
rw
rw
rw
rw
r/w
rw
rw
rw
rw
rw
rw
rw
rw
Table 66 - RegCntConfig1 register
Table 67 - RegCntConfig2 register
Reset
0
0
0
Reset
00
00
00
00
Reset
0
0
0
0
0
0
0
0
Table 68 - RegCntOn register
39
Function
1 = cascade counter A and B
0 = do not cascade counters A and B
1 = counter C (or C + D) PWM enabled
0 = counter C (or C + D) PWM disabled
1 = counter A (or A + B) PWM enabled
0 = counter A (or A + B) PWM disabled
Function
capture source selection
capture function selection
PWM1 size selection
PWM0 size selection
Function
1 = divide external clock PA[3] by 2
0 = do not divide
1 = divide external clock PA[2] by 2
0 = do not divide
1 = divide external clock PA[1] by 2
0 = do not divide
1 = divide external clock PA[0] by 2
0 = do not divide
1 = counter D enabled
0 = counter D disabled
1 = counter C enabled
0 = counter C disabled
1 = counter B enabled
0 = counter B disabled
1 = counter A enabled
0 = counter A disabled
SX1441 – Bluetooth® 1.2 SoC
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Data Sheet