EM250-BBRD-R Ember, EM250-BBRD-R Datasheet - Page 19

• Manufacturer Part Number: EM250-BBRD-R
• Description: EM250 BREAKOUT BOARD
• Manufacturer: Ember
• Type: Transceiver, 802.15.4r

Specifications of EM250-BBRD-R

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1024

4.4
4.5
Packet Trace Interface (PTI)
XAP2b Microprocessor
The primary features of the MAC are:
The EM250 integrates a true PHY-level PTI for effective network-level debugging. This two-signal interface
monitors all the PHY TX and RX packets (in a non-intrusive manner) between the MAC and baseband modules.
It is an asynchronous 500kbps interface and cannot be used to inject packets into the PHY/MAC interface. The
two signals from the EM250 are the frame signal (PTI_EN) and the data signal (PTI_DATA). The PTI is supported
by InSight Desktop.
The EM250 integrates the XAP2b microprocessor developed by Cambridge Consultants Ltd., making it a true
system-on-a-chip solution. The XAP2b is a 16-bit Harvard architecture processor with separate program and
data address spaces. The word width is 16 bits for both the program and data sides. Data-side addresses are
always specified in bytes, though they can be accessed as either bytes or words, while program-side addresses
are always specified and accessed as words. The data-side address bus is effectively 15 bits wide, allowing for
an address space of 32kB; the program-side address bus is 16 bits wide, addressing 64k words.
The standard XAP2 microprocessor and accompanying software tools have been enhanced to create the XAP2b
microprocessor used in the EM250. The XAP2b adds data-side byte addressing support to the XAP2 by utilizing
the 15
age of RAM, optimized code, and a more familiar architecture for Ember customers when compared to the
standard XAP2.
The XAP2b clock speed is 12MHz. When used with the EmberZNet stack, code is loaded into Flash memory over
the air or by a serial link using a built-in bootloader in a reserved area of the Flash. Alternatively, code may
be loaded via the SIF interface with the assistance of RAM-based utility routines also loaded via SIF.
The XAP2b in the EM250 has also been enhanced to support two separate protection levels. The EmberZNet
stack runs in System Mode, which allows full, unrestricted access to all areas of the chip, while application
code runs in Application Mode. When running in Application Mode, writing to certain areas of memory and reg-
isters is restricted to prevent common software bugs from interfering with the operation of the EmberZNet
stack. These errant writes are captured and details are reported to the developer to assist in tracking down
and fixing these issues.
CRC generation, appending, and checking
Hardware timers and interrupts to achieve the MAC symbol timing
Automatic preamble, and SFD pre-pended to a TX packet
Address recognition and packet filtering on received packets
Automatic acknowledgement transmission
Automatic transmission of packets from memory
Automatic transmission after backoff time if channel is clear (CCA)
Automatic acknowledgement checking
Time stamping of received and transmitted messages
Attaching packet information to received packets (LQI, RSSI, gain, time stamp, and packet status)
IEEE 802.15.4 timing and slotted/unslotted timing
th
bit of the data-side address bus to indicate byte or word accesses. This allows for more productive us-
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EM250
120-0082-000S