EM250-DEV Ember, EM250-DEV Datasheet - Page 65

• Manufacturer Part Number: EM250-DEV
• Description: KIT DEV FOR EM250
• Manufacturer: Ember
• Series: InSightr
• Type: 802.15.4/Zigbeer

Specifications of EM250-DEV

• Frequency: 2.4GHz
• For Use With/related Products: EM250
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 636-1002

the SPI serializer retransmits the last transmitted character or a busy token (
the register bit
Note: Even during a transmit underrun, the register bit
When a transmit character is written to the (empty) transmit FIFO, the
INT_SC2FLAG
is full, which causes the register bit
ter begins to clock data out of the MISO pin, the register bit
clears (after the first bit is clocked out) and indicates that not all characters are transmitted yet. After shift-
ing one full transmit character to the MISO pin, space for one transmit character becomes available in the
transmit FIFO. This causes the register bit
characters are shifted out, the transmit FIFO is empty, which causes the register bit
SC2_SPISTAT
The SPI Slave controller must guarantee that there is time to move new transmit data from the transmit FIFO
into the hardware serializer. To provide sufficient time, the SPI Slave controller inserts a byte of padding onto
the start of every new string of transmit data. After slave select asserts and the bit
SC2_SPISTAT
deasserts. Whenever the transmit FIFO is empty and data is placed into the transmit FIFO, either manually or
through DMA, the SPI hardware will insert an extra byte onto the front of the transmission as if this byte was
placed there by software. The value of the byte that is inserted is chosen by the bit
SC2_SPICFG
INT_SC2FLAG
Interrupts are generated by one of the following events:
To generate interrupts to the CPU, the interrupt masks in the
abled.
5.3.2
The SC2 I
3. The I
not implemented, so multiple master applications are not supported. The I
signals, and external pull-up resistors are required.
The SC2 I
Transmit FIFO empty and last character shifted out (0 to 1 transition of
Transmit FIFO changed from full to not full (0 to 1 transition of
Receive FIFO changed from empty to not empty (0 to 1 transition of
Transmit DMA buffer A/B complete (1 to 0 transition of
Receive DMA buffer A/B complete (1 to 0 transition of
Received and lost character while receive FIFO was full (Receive overrun error)
Transmitted character while transmit FIFO was empty (Transmit underrun error)
Programmable clock frequency (400kHz max.)
7- and 10-bit addressing
2
clear when the SPI master begins to clock data out of the MISO pin, indicating the transmitter is not
idle. After a complete byte has been clocked out, the bit
bit
INT_SCTXIDLE
I
C Master controller supports Standard (100kbps) and Fast (400kbps) I
2
2
2
C Master Mode
C controller is only available in master mode. The SC2 I
C mode has the following features:
INT_SCTXIDLE
. Take note that when this extra byte is transmitted, the bit
register do not change. Further transmit characters can be written to the transmit FIFO until it
register to be set.
register gets set at least once, the following operation will hold true until slave select
register.
SC_SPIRPT
will toggle in this manner for every byte that is transmitted as an underrun.
in the
in the
INT_SC2FLAG
SC2_SPICFG
SC_SPITXFREE
SC_SPITXFREE
register.
interrupt register will be set. The bits
in the
SC_SPITXIDLE
in the
SC2_SPISTAT
SC_RXACTA/B
SC_TXACTA/B
SC_SPITXIDLE
INT_SC2CFG
SC2_SPISTAT
2
SC_SPITXIDLE
C controller is enabled with
SC_SPITXFREE
SC2_SPISTAT
)
SC_SPIRXVAL
in the
register to clear. When the SPI mas-
INT_SCTXUND
)
2
and
C signals are pure open-collector
SC_SPITXIDLE
in the
0xFF
2
C modes. Address arbitration is
register to be set. After all
SC2_SPISTAT
INT_CFG
will be set and the register
), which is determined by
SC2_SPISTAT
)
SC_SPIRXVAL
SC_SPIRPT
SC_SPITXIDLE
register and the
SC_SPITXIDLE
)
will get set in the
register must be en-
120-0082-000I
)
register will
SC2_MODE
in the
EM250
register
in the
in the
and
set to
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