ATMEGA64RZAV-10PU Atmel, ATMEGA64RZAV-10PU Datasheet - Page 7

• Manufacturer Part Number: ATMEGA64RZAV-10PU
• Description: MCU ATMEGA644/AT86RF230 40-DIP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10PU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 40-DIP (0.600", 15.24mm)
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

4.3.2 Pull-up and Pull-down Configuration of Digital Input Pins
4.3.3 Register Description
5131E-MCU Wireless-02/09
Bit
0x03
Read/Write
Reset value
Bit
0x03
Read/Write
Reset value
Pulling resistors are internally connected to all digital input pins in radio transceiver
state P_ON (see section 7.1.2). Table 4-4 summarizes the pull-up and pull-down
configuration.
Table 4-4 Pull-Up/Pull-Down Configuration of Digital Input Pins in P_ON State
In all other radio transceiver states, no pull-up or pull-down resistors are connected to
any of the digital input pins.
Register 0x03 (TRX_CTRL_0)
The TRX_CTRL_0 register controls the drive current of the digital output pads and the
CLKM clock rate.
• Bit [7:6] – PAD_IO
The register bits PAD_IO set the output driver current of digital output pads MISO and
IRQ.
Table 4-5. Digital Output Driver Strength
• Bit [5:6] – PAD_IO_CLKM
The register bits PAD_IO_CLKM set the output driver current of pin CLKM.
Register Bit
PAD_IO
Notes:
CLKM_SHA_SEL
1. Reset values of register bits are underlined characterized in the document.
R/W
R/W
7
0
3
1
SLP_TR
Value
SCLK
MOSI
RST
SEL
Pin
PAD_IO
0
1
2
3
(1)
R/W
R/W
6
0
2
0
Description
2 mA
4 mA
6 mA
8 mA
CLKM_CTRL
R/W
R/W
5
0
1
0
PAD_IO_CLKM
H ≙ pull-up, L ≙ pull-down
R/W
R/W
AT86RF230
4
1
0
1
H
H
L
L
L
TRX_CTRL_0
TRX_CTRL_0
7