ATMEGA128RZAV-8AU Atmel, ATMEGA128RZAV-8AU Datasheet - Page 20

• Manufacturer Part Number: ATMEGA128RZAV-8AU
• Description: MCU ATMEGA1281/AT86RF230 64-TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RZAV-8AU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 64-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega128

6.5.2 Register Description
20
AT86RF230
Bit
0x0E
Read/Write
Reset value
Bit
0x0E
Read/Write
Reset value
Bit
0x0F
Read/Write
Reset value
Bit
0x0F
Read/Write
Reset value
Register 0x0E (IRQ_MASK)
The IRQ_MASK register is used to enable (set register bit to 1) or disable (set register
bit to 0) interrupt events by writing the corresponding bit to the interrupt mask register.
If an interrupt will be enabled or disabled, it is recommended to read the interrupt status
register 0x0F (IRQ_STATUS) first to clear the history.
Register 0x0F (IRQ_STATUS)
The IRQ_STATUS register contains the status of the individual interrupts. A read
access to this register resets all interrupt bits.
By reading the register after an interrupt is signaled at IRQ pin, the reason for the
interrupt can be identified.
A detailed description of the individual interrupts can be found in Table 6-8.
MASK_BAT_LOW MASK_TRX_UR
MASK_TRX_END MASK_RX_START MASK_PLL_UNLOCK MASK_PLL_LOCK
BAT_LOW
TRX_END
R/W
R/W
R
R
7
1
3
1
7
0
3
0
RX_START
TRX_UR
R/W
R/W
R
R
6
1
2
1
6
0
2
0
PLL_UNLOCK
R/W
R/W
R
R
5
1
1
1
5
0
1
0
Reserved
Reserved
PLL_LOCK
R/W
R/W
R
R
4
1
0
1
4
0
0
0
5131E-MCU Wireless-02/09
IRQ_STATUS
IRQ_STATUS
IRQ_MASK
IRQ_MASK