TRC103 RFM, TRC103 Datasheet - Page 12

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

The working length of the FIFO can set to 16, 32, 48 or 64 bytes through the MCFG05_FIFO_depth[7..6] register.
In the discussions below describing the FIFO behavior, the explanations are given with an assumption of 64
bytes, but the principle is the same for the four possible FIFO sizes.
The status of the FIFO can be monitored via interrupts which are described in Section 3.7. In addition to the
straightforward nFIFOEMPY and FIFOFULL interrupts, additional configurable interrupts Fifo_Int_Tx and
Fifo_Int_Rx are also available.
A low-to-high transition occurs on Fifo_Int_Rx when the number of bytes in the FIFO is greater than or equal to
the threshold set by MCFG05_FIFO_thresh[5..0] (number of bytes ≥ FIFO_thresh).
A low-to-high transition occurs on Fifo_Int_Tx when the number of bytes in the FIFO is less than or equal to the
threshold set by MCFG05_FIFO_thresh[5..0] (number of bytes ≤ FIFO_thresh).
3.1 Receiving in Continuous Data Mode
The receiver operates in continuous mode when the MCFG01_Mode[5] bit is set low. In this mode, the receiver
has two output signals indicating recovered clock, DCLK and recovered NRZ bit DATA. DCLK is connected to
output pin IRQ1 and DATA is connected to pin DATA configured in output mode. The data and clock recovery
controls the recovered clock signal, DCLK. Data and clock recovery is enabled by RXCFG12_DCLK_Dis[6] to 0
(default value). The clock recovered from the incoming data stream appears at DCLK. When data and clock re-
covery is disabled, the DCLK output is held low and the raw demodulator output appears at DATA. The function of
data and clock recovery is to remove glitches from the data stream and to provide a synchronous clock at DCLK.
The output DATA is valid at the rising edge of DCLK as shown in Figure 8.
Figure 7
As shown in Figure 7, the demodulator section includes the FSK demodulator, the OOK demodulator, data and
clock recovery and the start pattern detection blocks.
www.RFM.com
E-mail:
[e-mail]
Technical support +1.800.704.6079
Page 12 of 64
©2009-2010 by RF Monolithics, Inc.
TRC103 - 12/15/10