TRC103 RFM, TRC103 Datasheet - Page 23

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

expected length byte value of the received packet. If the length byte value of a received packet is greater than the
value in the PKTCFG1C_ Pkt_len[6..0] register, the packet is discarded. Otherwise the packet payload begins
loading into the FIFO.
If address match is enabled, the second byte received in a variable length mode or the first byte in the fixed length
mode is interpreted as the node address. If this address matches the byte in PKTCFG1D_Node_Addrs[7..0],
reception of the packet continues, otherwise it is stopped. A CRC check is performed if PKTCFG1E_CRC_
En[3] is set to 1. If the CRC check is successful, a 1 is loaded in the PKTCFG1E_CRC_stat[0] bit, and CRC_OK
and Dat_Rdy interrupts are simultaneously generated on IRQ1 and IRQ0 respectively. This signals that the pay-
load or balance of the payload can be read from the FIFO. In receive mode, address match, Dat_Rdy, and
CRC_OK interrupts and the CRC_stat bit are reset when the last byte in the FIFO is read. Note the FIFO can be
read in standby mode by setting PGCFG1F_ RnW_FIFO[6] bit to 1. In standby, reading the last FIFO byte does
not clear CRC_OK and the CRC_stat bit. They are reset once the TRC103 is put in receive mode again and a
start pattern is detected.
If the CRC check fails, the FIFO is cleared and no interrupts are generated. This action can be overridden by set-
ting PGCFG1F_CRCclr_auto[7] to 1, which forces a Data_Rdy interrupt and preserves the payload in the FIFO
even if the CRC fails.
3.9.5 Packet Filtering
Received packets can be filtered based on two criteria: length filtering and address filtering. In variable length or
extended variable length packet formats, PKTCFG1C_Pkt_len[6..0] stores the maximum payload length permit-
ted. If a received packet length byte is greater than this value, then the packet is discarded. Node address filtering
is enabled by setting parameter PKTCFG1E_Addrs_cmp[2..1] to any value other than 00, i.e., 01, 10 or 11.
These settings enable the following three options:
PKTCFG1E_Addrs_cmp[2..1] = 01: This configuration activates the node address filtering function on the
packet handler and the received address byte is compared with the address in the PKTCFG1D_Node_
Addrs[7..0] register. If both address bytes are the same, the received packet is for the current destination and is
stored in FIFO. Otherwise it is discarded. An interrupt can also be generated on IRQ0 if the address comparison
is successful.
PKTCFG1E_Addrs_cmp[2..1] = 10: In this configuration the received address is compared to both the
PKTCFG1D_Node_Addrs[7..0] register and constant 0x00. If the received node address byte matches either
value, the packet is accepted. An interrupt can also be generated on IRQ0 if the address comparison is success-
ful. The 0x00 address is useful for sending broadcast packets.
PKTCFG1E_Addrs_cmp[2..1] = 11: In this configuration the packet is accepted if the received node address
matches the PKTCFG1D_ Node_Addrs[7..0] register, 0x00 or 0xFF. An interrupt can also be generated on IRQ0
if the address comparison is successful. The 0x00 and 0xFF addresses are useful for sending two types of broad-
cast packets.
3.9.6 Cyclic Redundancy Check
The CRC check is enabled by setting the PKTCFG1E_CRC_En[3] bit to 1. A 16-bit CRC checksum is calculated
on the payload part of the packet and is appended to the end of the transmitted message. The CRC checksum is
calculated on the received payload and compared to the transmitted CRC. The result of the comparison is stored
in the PKTCFG1E_CRC_stat[0] bit and a CRC_OK interrupt can also be generated on IRQ1. The CRC is based
on the CCITT polynomial as shown in Figure 16. The CRC also detects errors due to leading and trailing zeros.
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TRC103 - 12/15/10