TRC103 RFM, TRC103 Datasheet - Page 52

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

The dual register set allows a new frequency to be completely entered in one register set while operating on the
other register set. It is important to load all three divider parameters into a register set before switching control to
it. Otherwise, a transient out-of-band frequency shift can occur. The dual register set facilitates FHSS operation,
as the operating frequency for the next hop can be loaded anytime during the current hop interval, making this
programming task less time critical. The values of P, S and R for FSK operation on several common frequencies
are given in Table 65. Software for determining P, S and R values for any in-band frequency is provided with the
TRC103 development kit.
6.5 Frequency Synthesizer Channel Programming for OOK Modulation
When using a standard 12.8 MHz reference crystal the RF channel frequency for OOK receive is:
Where F
must be less than (P+1). An F
quency F
MCFG00 bit 0 selects the register set to use for the frequency synthesizer. A 0 value selects register set MCFG06
- MCFG08 and a 1 value selects register set MCFG09 - MCFG0B. In addition, MCFG00 bits 4..3 select the oper-
ating band as follows:
The dual register set allows a new frequency to be completely entered in one register set while operating on the
other register set. It is important to load all three divider parameters into a register set before switching control to
it. Otherwise, a transient out-of-band frequency shift can occur. The dual register set facilitates FHSS operation,
as the operating frequency for the next hop can be loaded anytime during the current hop interval, making this
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F
TXRF
IF2
TXRF
. There are two sets of three registers that hold the values of P, S and R:
and transmitter deviation frequency F
E-mail:
= (14.4*(75*(P + 1) + S)/(R + 1)) - F
[e-mail]
DEV
MCFG00 bits 4..3
Configuration
value of 0.1 MHz is normally used, which must match the receiver low IF fre-
R
P
S
MCFG00 bits 4..3
MCFG0A
MCFG0B
Register
MCFG06
MCFG07
MCFG08
MCFG09
Technical support +1.800.704.6079
10
00
01
10
11
DEV
868.3 MHz
DEV
Table 65
, with P, S in the range 0 to 255, R in the range of 64 to 169
Table 66
Table 67
106
133
10
55
are in MHz, and P, S, and R are divider integers where S
Divider Parameter
863 - 870 MHz
902 - 915 MHz
915 - 928 MHz
950 - 960 MHz
915.0 MHz
not used
Band
100
119
R1
P1
S1
R2
P2
S2
01
50
955.0 MHz
10
62
50
71
TRC103 - 12/15/10
Page 52 of 64