TRC103 RFM, TRC103 Datasheet - Page 19

• Manufacturer Part Number: TRC103
• Description: RFIC TRANSCEIVER MULTI-CHANNEL F
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC103

• Frequency: 863MHz ~ 960MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Purpose
• Power - Output: 11dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 4mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1095-2

3.8 Buffered Clock Output
The buffered clock output is a signal derived from F
troller and is output on the CLKOUT pin. The OSCFG1B_Clkout_En[7] bit controls the CLKOUT pin. When this
bit is set to 1, CLKOUT is enabled, otherwise it is disabled. The output frequency of CLKOUT is defined by the
value of the OSCFG1B_Clk_freq[6..2] parameter which gives the frequency divider ratio applied to F
to Table 40 for programming details. Note: CLKOUT is disabled when the TRC103 is in sleep mode. If sleep
mode is used, the host microcontroller must have provisions to run from its own clock source.
3.9 Packet Data Modes
The TRC103 provides optional on-chip RX and TX packet handling features. These features ease the develop-
ment of packet oriented wireless communication protocols and free the MCU resources for other tasks. The op-
tions include enabling protocols based on fixed and variable packet lengths, data scrambling, CRC checksum cal-
culations, and received packet filtering. All the programmable parameters of the packet handler are accessible
through the PKTCFG configuration registers of the device. The packet handling mode is enabled when the regis-
ter bit MCFG01_Packet_Hdl_En[2] is set to 1.
The packet handler supports three types of packet formats: fixed length packets, variable length packets, and ex-
tended variable length packets. The PKTCFG1E_Pkt_mode[7] bit selects either the fixed or the variable length
packet formats.
3.9.1 Fixed Length Packet Mode
The fixed length packet mode is selected by setting the PKTCFG1E_Pkt_mode[7] bit to 0. In this mode the
length of the packet is set by the PKTCFG1C_Pkt_len[6..0] register up to the size of the FIFO which has been
selected. The length stored in this register is the length of the payload which includes the message data bytes
and optional address byte. The fixed length packet format shown in Figure 13 is made up of the following fields:
www.RFM.com
©2009-2010 by RF Monolithics, Inc.
1. Preamble
2. Start pattern (network address)
3. Node address byte (optional)
4. Data bytes
5. Two-byte CRC checksum (optional)
E-mail:
[e-mail]
Technical support +1.800.704.6079
XTAL
Figure 13
. It can be used as a reference clock for the host microcon-
TRC103 - 12/15/10
XTAL
Page 19 of 64
. Refer