ATMEGA256RZAV-8AU Atmel, ATMEGA256RZAV-8AU Datasheet - Page 144
![MCU ATMEGA2561/AT86RF230 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA256RZAV-8AU
Manufacturer Part Number
ATMEGA256RZAV-8AU
Description
MCU ATMEGA2561/AT86RF230 64-TQFP
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA256RZAV-8AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
ISM, ZigBee™
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-TQFP
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega256
- Current page: 144 of 444
- Download datasheet (10Mb)
16.6.1
16.6.2
16.6.3
2549M–AVR–09/10
Input Capture Trigger Source
Noise Canceler
Using the Input Capture Unit
The ICRn Register can only be written when using a Waveform Generation mode that utilizes
the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera-
tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn
Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location
before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to
on page
The main trigger source for the input capture unit is the Input Capture Pin (ICPn).
Timer/Counter1 can alternatively use the analog comparator output as trigger source for the
input capture unit. The Analog Comparator is selected as trigger source by setting the analog
Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The input capture flag
must therefore be cleared after the change.
Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled
using the same technique as for the Tn pin
identical. However, when the noise canceler is enabled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-
form Generation mode that uses ICRn to define TOP.
An input capture can be triggered by software by controlling the port of the ICPn pin.
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in
Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces addi-
tional four system clock cycles of delay from a change applied to the input, to the update of the
ICRn Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICRn Register before the next event occurs, the ICRn will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICRn
138.
ATmega640/1280/1281/2560/2561
(Figure 17-1 on page
169). The edge detector is also
“Accessing 16-bit Registers”
144
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