ATMEGA256RZAV-8AU Atmel, ATMEGA256RZAV-8AU Datasheet - Page 332
![MCU ATMEGA2561/AT86RF230 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA256RZAV-8AU
Manufacturer Part Number
ATMEGA256RZAV-8AU
Description
MCU ATMEGA2561/AT86RF230 64-TQFP
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA256RZAV-8AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
ISM, ZigBee™
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-TQFP
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega256
- Current page: 332 of 444
- Download datasheet (10Mb)
28.7
28.7.1
2549M–AVR–09/10
Register Description
SPMCSR – Store Program Memory Control and Status Register
Table 28-14. Read-While-Write Limit, ATmega2560/2561
Note:
Table 28-15. Explanation of different variables used in
Notes:
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
Bit
0x37 (0x57)
Read/Write
Initial Value
Section
Read-While-Write section (RWW)
No Read-While-Write section (NRWW)
Variable
PCMSB
PAGEMSB
ZPCMSB
ZPAGEMSB
PCPAGE
PCWORD
1. For details about these two section, see
1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
2. See
3. The Z-register is only 16 bits wide. Bit 16 is located in the RAMPZ register in the I/O map.
(1)
318
Z-pointer during Self-Programming.
ping to the Z-pointer, ATmega2560/2561
SPMIE
and
“Addressing the Flash During Self-Programming” on page 322
R/W
7
0
PC[16:7]
PC[6:0]
“RWW – Read-While-Write Section” on page
16
6
RWWSB
R
6
0
Corresponding
Z17:Z16
Z-value
ATmega640/1280/1281/2560/2561
Z17
SIGRD
R/W
Z7:Z1
5
0
Z7
(3)
:Z8
(2)
(3)
RWWSRE
R/W
4
0
Description
Most significant bit in the Program Counter. (The
Program Counter is 17 bits PC[16:0]).
Most significant bit which is used to address the
words within one page (128 words in a page
requires seven bits PC [6:0]).
Bit in Z-pointer that is mapped to PCMSB. Because
Z0 is not used, the ZPCMSB equals PCMSB + 1.
Bit in Z-pointer that is mapped to PCMSB. Because
Z0 is not used, the ZPAGEMSB equals PAGEMSB +
1.
Program Counter page address: Page select, for
Page Erase and Page Write.
Program Counter word address: Word select, for
filling temporary buffer (must be zero during Page
Write operation).
“NRWW – No Read-While-Write Section” on page
BLBSET
R/W
3
0
Figure 28-3 on page 322
Pages
992
32
(1)
318.
PGWRT
R/W
2
0
Address
0x00000 - 0x1EFFF
0x1F000 - 0x1FFFF
PGERS
for details about the use of
R/W
1
0
SPMEN
R/W
and the map-
0
0
SPMCSR
332
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