ATMEGA256RZAV-8AU Atmel, ATMEGA256RZAV-8AU Datasheet - Page 77
![MCU ATMEGA2561/AT86RF230 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA256RZAV-8AU
Manufacturer Part Number
ATMEGA256RZAV-8AU
Description
MCU ATMEGA2561/AT86RF230 64-TQFP
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA256RZAV-8AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
ISM, ZigBee™
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-TQFP
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega256
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2549M–AVR–09/10
Table 12-2
ure 12-5 on page 76
generated internally in the modules having the alternate function.
Table 12-2.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Signal Name
DIEOE
DIEOV
PUOE
DDOE
DDOV
PUOV
PVOE
PVOV
PTOE
AIO
DI
summarizes the function of the overriding signals. The pin and port indexes from
Generic Description of Overriding Signals for Alternate Functions
Pull-up Override
Pull-up Override
Override Enable
Override Enable
Override Enable
Enable Override
Enable Override
Override Value
Override Value
Data Direction
Data Direction
Input/Output
Digital Input
Digital Input
Digital Input
Port Toggle
Full Name
Port Value
Port Value
are not shown in the succeeding tables. The overriding signals are
Enable
Enable
Analog
Value
Value
ATmega640/1280/1281/2560/2561
If this signal is set, the pull-up enable is controlled by the PUOV
If this signal is set, the Output Driver Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable is
value is controlled by the PVOV signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
clock source, the module with the alternate function will use its
This is the Analog Input/output to/from alternate functions. The
This is the Digital Input to alternate functions. In the figure, the
If PVOE is set, the port value is set to PVOV, regardless of the
If PUOE is set, the pull-up is enabled/disabled when PUOV is
before the synchronizer. Unless the Digital Input is used as a
If this signal is set and the Output Driver is enabled, the port
set/cleared, regardless of the setting of the DDxn, PORTxn,
DIEOV is set/cleared, regardless of the MCU state (Normal
If DDOE is set, the Output Driver is enabled/disabled when
signal is connected directly to the pad, and can be used bi-
signal. If this signal is cleared, the pull-up is enabled when
DDOV is set/cleared, regardless of the setting of the DDxn
If this bit is set, the Digital Input Enable is controlled by the
If DIEOE is set, the Digital Input is enabled/disabled when
signal is connected to the output of the schmitt trigger but
DDOV signal. If this signal is cleared, the Output driver is
determined by MCU state (Normal mode, sleep mode).
If PTOE is set, the PORTxn Register bit is inverted.
setting of the PORTxn Register bit.
enabled by the DDxn Register bit.
{DDxn, PORTxn, PUD} = 0b010.
and PUD Register bits.
PORTxn Register bit.
mode, sleep mode).
own synchronizer.
Description
directionally.
Register bit.
Fig-
77
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