EM351-MOD-ANT-TG Ember, EM351-MOD-ANT-TG Datasheet - Page 184
![MODULE EM351 NO PA/LNA W/ANT TG](/photos/14/20/142076/em351-mod-ant-tg_sml.jpg)
EM351-MOD-ANT-TG
Manufacturer Part Number
EM351-MOD-ANT-TG
Description
MODULE EM351 NO PA/LNA W/ANT TG
Manufacturer
Ember
Specifications of EM351-MOD-ANT-TG
Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Power - Output
3dBm
Sensitivity
-100dBm
Voltage - Supply
2.1 V ~ 3.6 V
Current - Receiving
26mA
Current - Transmitting
31mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 12kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
Module
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Other names
636-1014
- Current page: 184 of 245
- Download datasheet (12Mb)
10.2
Interrupts
10.1.5.2 Input Range
The single-ended input range is fixed as 0 V to VREF and the differential input range is fixed as -VREF to
+VREF.
10.1.5.3 Sample Time
ADC sample time is programmed by selecting the sampling clock and the clocks per sample.
Table 10-4 shows the options for ADC sample times and the significant bits in the conversion results.
Note: ADC sample timing is the same whether the EM35x is using the 24 MHz crystal oscillator or the 12 MHz
high-speed RC oscillator. This facilitates using the ADC soon after the CPU wakes from deep sleep, before
switching to the crystal oscillator.
The ADC has its own top-level interrupt in the NVIC. The ADC interrupt is enabled by writing the INT_ADC bit
to the INT_CFGSET register, and cleared by writing the INT_ADC bit to the INT_CFGCLR register. Chapter 11,
Interrupt System, describes the interrupt system in detail.
Five kinds of ADC events can generate an ADC interrupt, and each has a bit flag in the INT_ADCFLAG register
to identify the reason(s) for the interrupt:
ADC_PERIOD
The sampling clock may be either 1 MHz or 6 MHz. If the ADC_1MHZCLK bit in the ADC_CFG register is
clear, the 6 MHz clock is used; if it is set, the 1 MHz clock is selected. The 6 MHz sample clock offers faster
conversion times but the ADC resolution is lower than that achieved with the 1 MHz clock.
The number of clocks per sample is determined by the ADC_PERIOD bits in the ADC_CFG register.
ADC_PERIOD values select from 32 to 4096 sampling clocks in powers of two. Longer sample times produce
more significant bits. Regardless of the sample time, converted samples are always 16-bits in size with the
significant bits left-aligned within the value.
INT_ADCOVF – an ADC conversion result was ready but the DMA was disabled (DMA buffer overflow).
INT_ADCSAT– the gain correction multiplication exceeded the limits for a signed 16-bit number (gain
saturation).
0
1
2
3
4
5
6
7
Sample
Clocks
1024
2048
4096
128
256
512
32
64
1 MHz clock
1024
2048
4096
128
256
512
32
64
Sample Time (µs)
Table 10-4. ADC Sample Times
Final
10-5
6 MHz clock
5.33
10.7
21.3
42.7
85.3
170
341
682
1 MHz clock
Sample Frequency (kHz)
0.977
0.488
0.244
31.3
15.6
7.81
3.91
1.95
6 MHz clock
EM351 / EM357
93.8
46.9
23.4
11.7
5.86
2.93
1.47
188
Significant Bits
120-035X-000G
10
11
12
13
14
7
8
9
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