ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 416
ATMEGA128RFA1-ZUR
Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
Specifications of ATMEGA128RFA1-ZUR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
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27.5.3 Conversion Timing
416
ATmega128RFA1
Figure 27-4. ADC Timing Diagram, Start-Up for Single Ended Channels
Figure 27-5. ADC Timing Diagram, Start-Up for Differential Channels
The delay from requesting a conversion start by setting the ADSC bit in ADCSRA to the
moment where the sample-and-hold takes place is fixed. The same fixed delay also
applies for auto triggered conversions. In this case three additional CPU clock cycles
are used for the trigger event synchronization logic. The delay depends on the
prescaler configuration ADPS and if single-ended or differential channels are used. A
summary is given in
When a conversion is complete, the result is written to the ADC Data Registers, and
ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software
may then set ADSC again, and a new conversion will be initiated at the earliest after the
following tracking phase. The tracking phase is required after each conversion. Its
duration can be adjusted according to the ADC clock speed by the ADTHT bits in
ADCSRC and is different for single-ended and differential channels. For details see
Table 27-4 on
In Free Running mode, a new conversion will be started immediately after the tracking
phase of the previous conversion while ADSC remains high. The calculation of the
resulting sample rate is given
For timing diagrams of single and auto triggered and free running conversions see
Figure 27-6 on
Table 27-3. Conversion Start Delay
A D C C lo c k
A D E N
A V D D O K
A D S C
A D IF
A D C H
A D C L
A D C C lo c k
A D E N
A V D D O K
A D S C
A D IF
A D C H
A D C L
Channel
Single-Ended
M U X a n d R E F S U p d a te
M U X a n d R E F S U p d a te
P o w e r -U p
P o w e r -U p
A V D D
t
A V D D
A V P U
t
A V P U
page 417.
page 417 to
Table 27-3
S ta rt - U p
S t a rt -U p
A D C
t
ADPS
0, 1
2
A D S U
A D C
t
A D S U
Figure 27-8 on
in Table 27-5 on
A m p lifie r
below. All conversions take 11 ADC clock cycles.
t
In it
A IN IT
Delay from Conversion Start Request to Sample &
Hold t
2 CPU clock cycles
4 CPU clock cycles
S a m p le
& H o ld
page 418.
SCSMP
1 1 T
C o n v e rs io n
S a m p le
& H o ld
page 417.
A D C _ C L K
C o n v e rs io n
C o m p le te
1 1 T
C o n v e r s io n
A D C _ C L K
C o n v e r s io n
C o m p le te
8266B-MCU Wireless-03/11
S ig n a n d M S B o f R e s u lt
L S B o f R e s u lt
S ig n a n d M S B
L S B o f R e s u lt
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