ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 417
![IC AVR MCU 2.4GHZ XCEIVER 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128RFA1-ZUR
Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
Specifications of ATMEGA128RFA1-ZUR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
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8266B-MCU Wireless-03/11
Table 27-4. Tracking Time
Table 27-5. Sample Rate in Free Running Mode
Figure 27-6. ADC Timing Diagram, Single Conversion
Figure 27-7. ADC Timing Diagram, Auto Triggered Conversion
A D C C lo c k
A D E N
A D S C
A D IF
A D C H
A D C L
A D C C lo ck
A D E N
T rig g e r S o u rce
A D A T E
A D IF
A D C H
A D C L
Channel
Differential
Channel
Single-Ended
Differential
Channel
Single-Ended
Differential
M U X a n d R E F S U p d a te
M U X a n d R E F S U p d a te
t
t
S C S M P
S C S M P
Tracking Phase Duration t
ADTHT+1, minimum 500 ns
2ADTHT+3
Sample Rate in ADC Clock Cycles
ADTHT+12
2ADTHT+14
ADPS
3
4…7
0…7
P re s ca le r R e s e t
a n d
S a m p le & H o ld
P re s ca le r R e se t
a n d
S a m p le & H o ld
1 1 T
1 1 T
C o n v e rsio n
C o n ve rs io n
A D C _ C L K
A D C _ C L K
Delay from Conversion Start Request to Sample &
Hold t
0 CPU clock cycles
0 CPU clock cycles
2 ADC clock cycles
C o n v e rsio n
C o n v e rsio n
C o m p le te
C o m p le te
SCSMP
TRCK
in ADC Clock Cycles
ATmega128RFA1
S ig n a n d M S B o f R e s u lt
L S B o f R e su lt
S ig n a n d M S B o f R e s u lt
L S B o f R e s u lt
T ra c kin g
T ra c k in g
M U X a n d R E F S U p d a te
M U X a n d R E F S U p d a te
t
t
T R C K
T R C K
t
t
S C S M P
S C S M P
C o n v e rs io n
C o n v e rs io n
P re s c a le r
R e se t
a n d
S a m p le
& H o ld
P re s ca le r
R e se t
a n d
S a m p le
& H o ld
417
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