SI1000-C-GM Silicon Laboratories Inc, SI1000-C-GM Datasheet - Page 180
![IC TXRX MCU + EZRADIOPRO](/photos/14/21/142131/42-qfn-series_sml.jpg)
SI1000-C-GM
Manufacturer Part Number
SI1000-C-GM
Description
IC TXRX MCU + EZRADIOPRO
Manufacturer
Silicon Laboratories Inc
Specifications of SI1000-C-GM
Package / Case
42-QFN
Frequency
240MHz ~ 960MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
General Purpose
Power - Output
20dBm
Sensitivity
-121dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
85mA
Data Interface
PCB, Surface Mount
Memory Size
64kB Flash, 4kB RAM
Antenna Connector
PCB, Surface Mount
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
240 MHz to 960 MHz
Interface Type
UART, SMBus, SPI, PCA
Output Power
20 dBm
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
4.1 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Protocol Supported
C2, SMBus
Core
8051
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
4352 B
Supply Current (max)
4.1 mA
Cpu Family
Si100x
Device Core
8051
Device Core Size
8b
Frequency (max)
25MHz
Total Internal Ram Size
4.25KB
# I/os (max)
22
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
18-chx10-bit
Instruction Set Architecture
CISC
Mounting
Surface Mount
Pin Count
42
Package Type
QFN EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1881-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI1000-C-GM
Manufacturer:
FSC
Quantity:
1 000
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Si1000/1/2/3/4/5
18.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The Comparator0 reset source remains func-
tional even when the device is in the low power Suspend and Sleep states as long as Comparator0 is also
enabled as a wake-up source. The state of the RST pin is unaffected by this reset.
18.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “28.4. Watchdog Timer Mode” on
page 363; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The PCA Watchdog Timer reset source is automatically disabled when the device is in the low
power Suspend or Sleep mode. Upon exit from either low power state, the enabled/disabled state of this
reset source is restored to its previous value.The state of the RST pin is unaffected by this reset.
18.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
18.8. SmaRTClock (Real Time Clock) Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRT-
Clock Alarm. The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock Detector
is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm event occurs
when the SmaRTClock Alarm is enabled and the SmaRTClock timer value matches the ALARMn regis-
ters. The SmaRTClock can be configured as a reset source by writing a 1 to the RTC0RE flag (RST-
SRC.7). The SmaRTClock reset remains functional even when the device is in the low power Suspend or
Sleep mode. The state of the RST pin is unaffected by this reset.
18.9. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
180
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the Lock Byte address.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“13.3. Security Options” on page 143).
A Flash write or erase is attempted while the V
Rev. 1.0
DD
Monitor is disabled.
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