SI1000-C-GM Silicon Laboratories Inc, SI1000-C-GM Datasheet - Page 299

• Manufacturer Part Number: SI1000-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1000-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 20dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 85mA
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 20 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Cpu Family: Si100x
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 25MHz
• Total Internal Ram Size: 4.25KB
• # I/os (max): 22
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 18-chx10-bit
• Instruction Set Architecture: CISC
• Mounting: Surface Mount
• Pin Count: 42
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1881-5

24.4.4. Limitations for Hardware Acknowledge Feature
In some system management bus (SMBus) configurations, the Hardware Acknowledge mechanism of the
SMBus peripheral can cause incorrect or undesired behavior. The Hardware Acknowledge mechanism is
enabled when the EHACK bit (SMB0ADM.0) is set to logic 1.
The configurations to which these limitations do not apply are as follows:
These limitations only apply to the following configurations:
The following issues are present when operating as a slave in a multi-slave SMBus configuration:
Impact :
a. All SMBus configurations when Hardware Acknowledge is disabled.
b. All single-master/single-slave SMBus configurations when Hardware Acknowledge is enabled
c. All multi-master/single-slave SMBus configurations when Hardware Acknowledge is enabled
d. All single-master/multi-slave SMBus configurations when Hardware Acknowledge is enabled
a. All multi-slave SMBus configurations when Hardware Acknowledge is enabled and the MCU is
b. All multi-master SMBus configurations when Hardware Acknowledge is enabled and the MCU
a. When Hardware Acknowledge is enabled and SDA setup and hold times are not extended
b. When Hardware Acknowledge is enabled and SDA setup and hold times are extended 
c. When Hardware Acknowledge is enabled and the ACK bit (SMB0CN.1) is set to 1, an
a. Once the CPU enters the interrupt service routine, SCL will be asserted low until SI is cleared,
b. Once the hardware has matched an address and entered the interrupt service routine, the
c. The SMBus master and the addressed slave are prevented from generating a NACK by the
and the MCU is operating as a master or slave .
and the MCU is operating as a slave .
and the MCU is operating as a master .
operating as a slave .
is operating as a master .
(EXTHOLD = 0 in the SMB0CF register), the SMBus hardware will always generate an SMBus
interrupt following the ACK/NACK cycle of any slave address transmission on the bus, whether
or not the address matches the conditions of SMB0ADR and SMB0MASK. The expected
behavior is that an interrupt is only generated when the address matches.
(EXTHOLD = 1 in the SMB0CF register), the SMBus hardware will only generate an SMBus
interrupt as expected when the slave address transmission on the bus matches the conditions of
SMB0ADR and SMB0MASK. However, in this mode, the Start bit (STA) will be incorrectly
cleared on reception of a slave address before software vectors to the interrupt service routine.
unaddressed slave may cause interference on the SMBus by driving SDA low during an ACK
cycle. The ACK bit of the unaddressed slave may be set to 1 if any device on the bus generates
an ACK.
causing the clock to be stretched when the MCU is not being addressed. This may limit the
maximum speed of the SMBus if the master supports SCL clock stretching. Incompliant SMBus
masters that do not support SCL clock stretching will not recognize that the clock is being
stretched. If the CPU issues a write to SMB0DAT, it will have no effect on the bus. No data
collisions will occur.
firmware will not be able to use the Start bit to distinguish between the reception of an address
byte versus the reception of a data byte. However, the hardware will still correctly acknowledge
the address byte (SLA+R/W).
unaddressed slave because it is holding SDA low during the ACK cycle. There is a potential for
the SMBus to lock up.
Rev. 1.0
Si1000/1/2/3/4/5
299