MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet - Page 53

IC MIFARE READER 32-HVQFN

MFRC52301HN1,151

Manufacturer Part Number
MFRC52301HN1,151
Description
IC MIFARE READER 32-HVQFN
Manufacturer
NXP Semiconductors
Series
MIFARE®r
Datasheets

Specifications of MFRC52301HN1,151

Frequency
13.56MHz
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Operating Current
7 mA
Operating Voltage
2.5 V to 3.6 V
Product
RFID Readers
Wireless Frequency
13.56 MHz
Interface Type
RS-232, I2C
Data Rate
100 Kbps
Operating Temperature Range
- 25 C to +85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Rf Type
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4766
935282956151
MFRC52301HN1
NXP Semiconductors
MFRC523_34
Product data sheet
PUBLIC
9.2.2.16 SerialSpeedReg register
Table 81.
Selects the speed of the serial UART interface.
Table 82.
Table 83.
Bit
4
3
2
1 to 0
Bit
Symbol
Access
Bit
7 to 5
4 to 0
Symbol
EOFSOFWidth 1
NoTxSOF
NoTxEOF
TxEGT
Symbol
BR_T0[2:0]
BR_T1[4:0]
TypeBReg register bit descriptions
SerialSpeedReg register (address 1Fh); reset value: EBh bit allocation
SerialSpeedReg register bit descriptions
7
All information provided in this document is subject to legal disclaimers.
BR_T0[2:0]
Rev. 3.5 — 24 September 2010
R/W
6
Value Description
0
1
1
00
01
10
11
Description
factor BR_T0 adjusts the transfer speed: for description, see
Section 8.3.3.2 on page 12
factor BR_T1 adjusts the transfer speed: for description, see
Section 8.3.3.2 on page 12
115235
if this bit is set to logic 1 and EOFSOFAdjust bit (AutoTestReg
register) is logic 0, the SOF and EOF will have the maximum
length defined in ISO/IEC 14443 B.
if this bit is set to logic 1 and the EOFSOFAadjust bit is logic 1:
then
if this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF
and EOF will have the minimum length defined in
ISO/IEC 14443 B.
if this bit is set to logic 0 and the EOFSOFAdjust bit is logic 1
results in an incorrect system behavior in respect to ISO
specification
SOF is suppressed
EOF is suppressed
defines EGT bit length
SOF low = (11 ETU − 8 cycles) / f
SOF high = (2 ETU + 8 cycles) / f
EOF low = (11 ETU − 8 cycles) / f
no bits
1 bit
2 bits
3 bits
5
4
…continued
3
BR_T1[4:0]
R/W
clk
clk
clk
2
Contactless reader IC
MFRC523
© NXP B.V. 2010. All rights reserved.
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