SLRC40001T/OFE,112 NXP Semiconductors, SLRC40001T/OFE,112 Datasheet
SLRC40001T/OFE,112
Specifications of SLRC40001T/OFE,112
935269551112
SLRC400
SLRC41TOFED
Related parts for SLRC40001T/OFE,112
SLRC40001T/OFE,112 Summary of contents
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SLRC400 ICODE reader IC Rev. 3.3 — 23 March 2010 054333 1. Introduction This data sheet describes the functionality of the SLRC400 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system and hardware viewpoint gives ...
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... NXP Semiconductors Software controlled Power-down mode Programmable timer Unique serial number User programmable start-up configuration Bit-oriented and byte oriented framing Independent power supply pins for analog, digital and transmitter modules Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz ...
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... NXP Semiconductors 6. Block diagram NWR NRD NCS ALE PARALLEL INTERFACE CONTROL (INCLUDING AUTOMATIC INTERFACE DETECTION AND SYNCHRONISATION) FIFO CONTROL 64-BYTE FIFO CONTROL REGISTER BANK EEPROM 8 × 16-BYTE ACCESS EEPROM CONTROL MASTER KEY BUFFER CRYPTO1 UNIT 32-BIT PSEUDO RANDOM GENERATOR AMPLITUDE RATING ...
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... NXP Semiconductors 7. Pinning information Fig 2. 7.1 Pin description Table 2. Pin description Pin Symbol Type 1 OSCIN I 2 IRQ SIGOUT O 5 TX1 O 6 TVDD P 7 TX2 O 8 TVSS G 9 NCS I [2] 10 NWR I R/NW I nWrite I [2] 11 NRD I NDS I nDStrb I SLRC400_33 Product data sheet ...
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... NXP Semiconductors Table 2. Pin description …continued Pin Symbol Type 12 DVSS G [ I/O AD0 to AD7 I/O [2] 21 ALE nAStrb I [ nWait DVDD P 26 AVDD P 27 AUX O 28 AVSS VMID P 31 RSTPD I 32 OSCOUT O [1] Pin types Input Output, I/O = Input/Output Power and G = Ground. [2] These pins provide different functionality depending on the selected microprocessor interface type (see detailed information) ...
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... NXP Semiconductors 8. Functional description 8.1 Digital interface 8.1.1 Overview of supported microprocessor interfaces The SLRC400 supports direct interfacing to various 8-bit microprocessors. Alternatively, the SLRC400 can be connected to a PC’s Enhanced Parallel Port (EPP). the parallel interface signals supported by the SLRC400. Table 3. Bus control signals ...
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... NXP Semiconductors 8.1.3 Connection to different microprocessor types The connection to various microprocessor types is shown in Table 4. SLRC400 pins ALE NRD NWR NCS 8.1.3.1 Separate read and write strobe address bus (A3 to An) ADDRESS DECODER address bus (A0 to A2) data bus (D0 to D7) HIGH Read strobe (NRD) Write strobe (NWR) Fig 3 ...
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... NXP Semiconductors 8.1.3.2 Common read and write strobe address bus (A3 to An) ADDRESS DECODER address bus (A0 to A2) data bus (D0 to D7) HIGH Data strobe (NDS) Read/Write (R/NW) Fig 4. Connection to microprocessor: common read and write strobes Refer to 8.1.3.3 Common read and write strobe: EPP with handshake Fig 5 ...
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... NXP Semiconductors 8.2 Memory organization of the EEPROM Table 5. Block Position Remark recommend to use only the above EEPROM address area. 8.2.1 Product information field (read only) Table 6. Product information field byte allocation Byte 15 14 Symbol CRC RsMaxP Access R R Table 7. Product information field ...
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... NXP Semiconductors Table 8. Definition Byte Value [1] Byte 4 contains the current version number. 8.2.2 Register initialization file (read/write) Register initialization from address 10h to address 2Fh is performed automatically during the initializing phase (see initialization file. In addition, the SLRC400 registers can be initialized using values from the StartUp ...
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... NXP Semiconductors Table 10. Shipment content of StartUp register initialization file EEPROM Register Value Symbol byte address address 10h 10h 00h Page 11h 11h 58h TxControl 12h 12h 3Fh CwConductance 13h 13h 05h ModGsCfg 14h 14h 2Ch CoderControl 15h 15h 3Fh ModWidth 16h ...
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... NXP Semiconductors 8.2.2.3 Register initialization file (read/write) The EEPROM memory content from block address can initialize register sub addresses 10h to 2Fh when the LoadConfig command is executed (see page 75). This command requires the EEPROM starting byte address as a two byte argument for the initialization procedure. ...
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... NXP Semiconductors Table 12. Active command Transceive WriteE2 ReadE2 LoadConfig CalcCRC 8.3.2 Controlling the FIFO buffer In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO buffer to be written with another 64 bytes of data ...
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... NXP Semiconductors Table 13. Flags FIFOLength[6:0] FIFOOvfl FlushFIFO HiAlert HiAlertIEn HiAlertIRq LoAlert LoAlertIEn LoAlertIRq WaterLevel[5:0] 8.4 Interrupt request system The SLRC400 indicates interrupt events by setting the PrimaryStatus register bit IRq (see Section 9.5.1.4 “PrimaryStatus register” on page pin IRQ can be used to interrupt the microprocessor using its interrupt handling capabilities ensuring efficient microprocessor software ...
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... NXP Semiconductors Table 14. Interrupt flag TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq 8.4.2 Interrupt request handling 8.4.2.1 Controlling interrupts and getting their status The SLRC400 informs the microprocessor about the interrupt request source by setting the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as source for an interrupt can be masked by the InterruptEn register interrupt enable bits ...
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... NXP Semiconductors • bit IRQPushPull: when set to logic 1, pin IRQ has CMOS output characteristics. When it is set to logic open-drain output which requires an external resistor to achieve a HIGH-level at pin IRQ. Remark: During the reset phase (see logic 1 and bit IRQPushPull is set to logic 0. This results in a high-impedance on pin IRQ. ...
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... NXP Semiconductors 8.5.1 Timer unit implementation 8.5.1.1 Timer unit block diagram Figure 6 Fig 6. The timer unit is designed, so that events when combined with enabling flags start or stop the counter. For example, setting bit TStartTxBegin = logic 1 enables control of received data with the timer unit. In addition, the first received bit is indicated by the TxBegin event. ...
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... NXP Semiconductors The timer is started immediately by loading a value from the TimerReload register into the counter module. This is activated by one of the following events: • transmission of the first bit to the label (TxBegin event) with bit TStartTxBegin = logic 1 • transmission of the last bit to the label (TxEnd event) with bit TStartTxEnd = logic 1 • ...
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... NXP Semiconductors 8.5.1.4 Timer unit status The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start events start the timer at the TReloadValue[7:0] and changes the status flag TRunning to logic 1. Conversely, configured stop events stop the timer and sets the TRunning status flag to logic 0 ...
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... NXP Semiconductors Table 17. ICODE1 mode standard mode fast mode Remark: Set bit TxCRCEn to logic 0 before the Quit frame is sent. If TxCRCEn is not set to logic 0, the Quit frame is sent with a calculated CRC value. Use the CRC8 algorithm to calculate the Quit value. 8.5.2 Using the timer unit functions 8 ...
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... NXP Semiconductors Table 18. Flags TStartTxBegin TStartTxEnd TStopNow TStopRxBegin TStopRxEnd 8.6 Power reduction modes 8.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself) ...
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... NXP Semiconductors After resetting the Control register bit PowerDown, the bit indicating Soft power-down mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The PowerDown bit is automatically cleared when the Soft power-down mode is exited. Remark: When the internal oscillator is used, time (t become stable ...
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... NXP Semiconductors 8.7.2 Reset phase The reset phase automatically follows the Hard power-down. Once the oscillator is running stably, the reset phase takes 512 clock cycles. During the reset phase, some register bits are preset by hardware. The respective reset values are given in the ...
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... NXP Semiconductors 8.8 Oscillator circuit Fig 9. The clock applied to the SLRC400 acts as a time basis for the synchronous system encoder and decoder. The stability of the clock frequency is an important factor for correct operation. To obtain highest performance, clock jitter must be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry ...
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... NXP Semiconductors Table 21. TxControl register configuration TX2RFEn 8.9.2 Antenna operating distance versus power consumption Using different antenna matching circuits (by varying the supply voltage on the antenna driver supply pin TVDD possible to find the trade-off between maximum effective operating distance and power consumption. Different antenna matching circuits are described in the Application note 8 ...
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... NXP Semiconductors 8.9.3.1 Source resistance table Table 22. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW MANT = Mantissa; EXP = Exponent. GsCfgCW EXP MANT GsCfgCW (decimal) (decimal) (decimal 8.9.3.2 Changing the modulation index Table Table 23 resistance (R 00h and 3Fh. Note that if the modulation index value is changed the GsCfgMod[5:0] value must also be changed ...
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... NXP Semiconductors Table 23. Modulation index values GsCfgMod[5:0] Relative (Hex) resistance during modulation (Ω) ∝ 00 ∝ 10 ∝ 20 ∝ 0.522 02 0.5 03 0.333 21 0.27 12 0.261 04 0.25 05 0.2 13 0.174 06 0.167 07 0.143 31 0.14 22 0.135 14 0.13 08 0.125 09 0.111 15 0.104 0A 0.1 0B 0.091 23 0.090 16 0.087 0C 0.083 0D 0.077 17 0.075 0E 0.071 32 0 ...
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... NXP Semiconductors 8.9.3.3 Calculating the relative source resistance The reference source resistance ref 8.9.3.4 Calculating the effective source resistance Wiring resistance (R resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The additional resistance for pin TX1 (R Equation R ( )TX1 S wire ...
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... NXP Semiconductors The demodulated signal is amplified by an adjustable amplifier. A correlation circuit calculates the degree of similarity between the expected and the received signal. The BitPhase register enables correlation interval position alignment with the received signal’s bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital results are sent to the FIFO buffer ...
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... NXP Semiconductors Fig 11. Automatic Q-clock calibration Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or approximately 4.8 μs. The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the phase-shift between the Q-clock and the I-clock is greater than 180° ...
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... NXP Semiconductors The correlation circuitry needs the phase information for the incoming label signal for optimum performance. This information is defined for the microprocessor using the BitPhase register. This value defines the phase relationship between the transmitter and receiver clock in multiples of the BitPhase time (t 8 ...
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... NXP Semiconductors MILLER CODER 1 OUT OF 256 serial data out OUT OF 4 (part of) serial data processing MANCHESTER serial data in DECODER SERIAL SIGNAL SWITCH Fig 12. Serial signal switch block diagram Section 8.11.2 the serial signal switch. 8.11.2 Serial signal switch registers The RxControl2 register DecoderSource[1:0] bits define the input signal for the internal Manchester decoder and are described in Table 25 ...
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... NXP Semiconductors Table 26. See Table 86 on page 54 Number The SIGOUTSelect register’s SIGOUTSelect[2:0] bits select the input signal to be routed to the internal Manchester decoder. Table 27. See Table 100 on page 57 Number Remark: To use the SIGOUTSelect[2:0] bits, the TestDigiSelect register SignalToSIGOUT bit must be logic 0. ...
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... NXP Semiconductors 9. SLRC400 registers 9.1 Register addressing modes Three methods can be used to operate the SLRC400: • initiating functions and controlling data by executing commands • configuring the functional operation using a set of configuration bits • monitoring the state of the SLRC400 by reading status flags The commands, configuration bits and flags are accessed using the microprocessor interface ...
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... NXP Semiconductors Table 30. Abbreviation R SLRC400_33 Product data sheet PUBLIC Behavior and designation of register bits Behavior Description read and write These bits can be read and written by the microprocessor. Since they are only used for control, their content is not influenced by internal state machines. ...
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... NXP Semiconductors 9.3 Register overview Table 31. SLRC400 register overview Sub Register name address (Hex) Page 0: Command and status 00h Page 01h Command 02h FIFOData 03h PrimaryStatus 04h FIFOLength 05h SecondaryStatus 06h InterruptEn 07h InterruptRq Page 1: Control and status 08h Page 09h ...
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... NXP Semiconductors Table 31. SLRC400 register overview Sub Register name address (Hex) Page 4: RF Timing and channel redundancy 20h Page 21h RxWait 22h ChannelRedundancy 23h CRCPresetLSB 24h CRCPresetMSB 25h TimeSlotPeriod 26h SIGOUTSelect 27h PreSet27 Page 5: FIFO, timer and IRQ pin configuration 28h ...
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... NXP Semiconductors 9.4 SLRC400 register flags overview Table 32. Flag(s) AccessErr BitPhase[7:0] ClkQ180Deg ClkQCalib ClkQDelay[4:0] CollErr CollLevel[3:0] CollPos[7:0] Command[5:0] CRC3309 CRC8 CRCErr CRCMSBFirst CRCPresetLSB[7:0] CRCPresetMSB[7:0] CRCReady CRCResultMSB[7:0] CRCResultLSB[7:0] DecoderSource[1:0] E2Ready Err FIFOData[7:0] FIFOLength[6:0] FIFOOvfl FlushFIFO FramingErr Gain[1:0] GsCfgCW[5:0] GsCfgMod[5:0] HiAlert HiAlertIEn HiAlertIRq ...
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... NXP Semiconductors Table 32. Flag(s) LoAlertIEn LoAlertIRq SIGOUTSelect[2:0] MinLevel[3:0] ModemState[2:0] ModulatorSource[1:0] ModWidth[7:0] PageSelect[2:0] PowerDown RcvClkSelI RxAutoPD RxCRCEn RxIEn RxIRq RxLastBits[2:0] RxWait[7:0] SetIEn SetIRq SignalToSIGOUT StandBy TAutoRestart TestAnaOutSel[4:0] TestDigiSignalSel[6:0] TimerIEn TimerIRq TimerValue[7:0] TPreScaler[4:0] TReloadValue[7:0] TRunning TStartTxBegin TStartTxEnd TStartNow TStopRxBegin TStopRxEnd TStopNow TX1RFEn TX2Cw ...
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... NXP Semiconductors Table 32. Flag(s) TxIEn TxIRq TxLastBits[2:0] UsePageSelect WaterLevel[5:0] ZeroAfterColl 9.5 Register descriptions 9.5.1 Page 0: Command and status 9.5.1.1 Page register Selects the page register. Table 33. Bit Symbol Access Table 34. Bit 9.5.1.2 Command register Starts and stops the command execution. Table 35. ...
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... NXP Semiconductors Table 36. Bit 9.5.1.3 FIFOData register Input and output of the 64 byte FIFO buffer. Table 37. Bit Symbol Access Table 38. Bit 9.5.1.4 PrimaryStatus register Bits relating to receiver, transmitter and FIFO buffer status flags. Table 39. Bit Symbol Access SLRC400_33 Product data sheet PUBLIC ...
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... NXP Semiconductors Table 40. Bit Symbol ModemState[2:0] 3 IRq 2 Err 1 HiAlert 0 LoAlert 9.5.1.5 FIFOLength register Number of bytes in the FIFO buffer. Table 41. Bit Symbol Access SLRC400_33 Product data sheet PUBLIC PrimaryStatus register bit descriptions Value Status - 000 Idle 001 TxSOF 010 TxData 011 TxEOF ...
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... NXP Semiconductors Table 42. Bit Symbol FIFOLength[6:0] 9.5.1.6 SecondaryStatus register Various secondary status flags. Table 43. Bit Symbol Access Table 44. Bit 9.5.1.7 InterruptEn register Control bits to enable and disable passing of interrupt requests. Table 45. Bit Symbol Access Table 46. Bit Symbol 7 SetIEn TimerIEn 4 TxIEn 3 RxIEn ...
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... NXP Semiconductors Table 46. Bit Symbol 2 IdleIEn 1 HiAlertIEn - 0 LoAlertIEn - [1] This bit can only be set or cleared using bit SetIEn. 9.5.1.8 InterruptRq register Interrupt request flags. Table 47. Bit Symbol Access Table 48. Bit Symbol 7 SetIRq TimerIRq 4 TxIRq 3 RxIRq 2 IdleIRq 1 HiAlertIRq 0 LoAlertIRq [1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq. ...
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... NXP Semiconductors 9.5.2 Page 1: Control and status 9.5.2.1 Page register Selects the page register; see 9.5.2.2 Control register Various control flags, for timer, power saving, etc. Table 49. Bit Symbol Access Table 50. Bit 9.5.2.3 ErrorFlag register Error flags show the error status of the last executed command. ...
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... NXP Semiconductors Table 52. Bit Symbol 2 FramingErr CollErr 9.5.2.4 CollPos register Bit position of the first bit-collision detected on the RF interface. Table 53. Bit Symbol Access Table 54. Bit 9.5.2.5 TimerValue register Value of the timer. Table 55. Bit Symbol Access Table 56. Bit 9.5.2.6 CRCResultLSB register LSB of the CRC coprocessor register. ...
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... NXP Semiconductors Table 57. Bit Symbol Access Table 58. Bit 9.5.2.7 CRCResultMSB register MSB of the CRC coprocessor register. Table 59. Bit Symbol Access Table 60. Bit 9.5.2.8 BitFraming register Adjustments for bit oriented frames. Table 61. Bit Symbol Access SLRC400_33 Product data sheet PUBLIC CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit ...
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... NXP Semiconductors Table 62. Bit Symbol RxAlign[2: TxLastBits[2:0] 9.5.3 Page 2: Transmitter and control 9.5.3.1 Page register Selects the page register; see 9.5.3.2 TxControl register Controls the logical behavior of the antenna pin TX1 and TX2. Table 63. Bit Symbol Access Table 64. Bit SLRC400_33 Product data sheet ...
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... NXP Semiconductors Table 64. Bit 9.5.3.3 CwConductance register Selects the conductance of the antenna driver pins TX1 and TX2. Table 65. Bit Symbol Access Table 66. Bit See Section 8.9.3 on page 25 9.5.3.4 ModConductance register Defines the driver output conductance. Table 67. Bit Symbol Access Table 68. ...
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... NXP Semiconductors 9.5.3.5 CoderControl register Sets the clock rate and the coding mode. Table 69. Bit Symbol Access Table 70. Bit Symbol 7 SendOnePulse CoderRate[2: TxCoding[2:0] SLRC400_33 Product data sheet PUBLIC CoderControl register (address: 14h) reset value: 0010 1100b, 2Ch bit allocation 7 6 SendOnePulse ...
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... NXP Semiconductors 9.5.3.6 ModWidth register Selects the pulse-modulation width. Table 71. Bit Symbol Access Table 72. Bit 9.5.3.7 ModWidthSOF register Table 73. Bit Symbol Access Table 74. Bit Symbol ModWidthSOF 9.5.3.8 PreSet17 register These bit values must not be changed. Table 75. Bit Symbol Access 9.5.4 Page 3: Receiver and decoder control 9.5.4.1 Page register Selects the page register ...
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... NXP Semiconductors Table 76. Bit Symbol Access Table 77. Bit Symbol SubCPulses[2: 010 2 LPOff Gain[1:0] 9.5.4.3 DecoderControl register Controls decoder operation. Table 78. Bit Symbol Access Table 79. Bit Symbol RxMultiple 5 ZeroAfterColl SLRC400_33 Product data sheet PUBLIC RxControl1 register (address: 19h) reset value: 1000 1011b, 8Bh bit allocation ...
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... NXP Semiconductors Table 79. Bit Symbol RxFraming[1:0] 2 RxInvert 9.5.4.4 BitPhase register Selects the bit-phase between transmitter and receiver clock. Table 80. Bit Symbol Access Table 81. Bit 9.5.4.5 RxThreshold register Selects thresholds for the bit decoder. Table 82. Bit Symbol Access Table 83. Bit 9.5.4.6 PreSet1D register These values must not be changed ...
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... NXP Semiconductors Table 84. Bit Symbol Access 9.5.4.7 RxControl2 register Controls decoder operation and defines the input source for the receiver. Table 85. Bit Symbol Access Table 86. Bit [1] I-clock and Q-clock are 90° phase-shifted from each other. 9.5.4.8 ClockQControl register Controls clock generation for the 90° phase-shifted Q-clock. ...
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... NXP Semiconductors Table 88. Bit 9.5.5 Page 4: RF Timing and channel redundancy 9.5.5.1 Page register Selects the page register; see 9.5.5.2 RxWait register Selects the time interval after transmission, before the receiver starts. Table 89. Bit Symbol Access Table 90. Bit 9.5.5.3 ChannelRedundancy register Selects the type and mode of checking the RF channel data integrity ...
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... NXP Semiconductors Table 92. Bit Symbol 5 CRC3309 4 CRC8 3 RxCRCEn 2 TxCRCEn [1] When used with ISO/IEC 15693, this bit must be set to logic 0. 9.5.5.4 CRCPresetLSB register LSB of the preset value for the CRC register. Table 93. Bit Symbol Access Table 94. Bit [1] To use the ISO/IEC 15693 functionality, the CRCPresetLSB register has to be set to FFh. ...
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... NXP Semiconductors Table 96. Bit Symbol CRCPresetMSB[7:0] [1] This register is not relevant if CRC8 is set to logic 1. 9.5.5.6 TimeSlotPeriod register Defines the time-slot period for ICODE1 protocol. Table 97. Bit Symbol Access Table 98. Bit 9.5.5.7 SIGOUTSelect register Selects the internal signal applied to pin SIGOUT. Table 99. ...
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... NXP Semiconductors Table 100. SIGOUTSelect register bit descriptions Bit Symbol SIGOUTSelect[2:0] 9.5.5.8 PreSet27 register These bit values must not be changed. Table 101. PreSet27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation Bit Symbol Access 9.5.6 Page 5: FIFO, timer and IRQ pin configuration 9.5.6.1 Page register Selects the page register ...
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... NXP Semiconductors Table 104. TimerClock register (address: 2Ah) reset value: 0000 1011b, 0Bh bit allocation Bit Symbol Access Table 105. TimerClock register bit descriptions Bit 9.5.6.4 TimerControl register Selects start and stop conditions for the timer. Table 106. TimerControl register (address: 2Bh) reset value: 0000 0010b, 02h bit allocation ...
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... NXP Semiconductors Table 108. TimerReload register (address: 2Ch) reset value: 0000 0000b, 00h bit allocation Bit Symbol Access Table 109. TimerReload register bit descriptions Bit Symbol TReloadValue[7:0] 9.5.6.6 IRQPinConfig register Configures the output stage for pin IRQ. Table 110. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation ...
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... NXP Semiconductors 9.5.7.2 Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h These registers are reserved for future use. Table 114. Reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: 0000 Bit Symbol Access 9.5.8 Page 7: Test control 9.5.8.1 Page register Selects the page register ...
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... NXP Semiconductors Table 117. TestAnaSelect bit descriptions Bit 9.5.8.4 PreSet3B register These register bit values must not be changed. Table 118. Reserved register (address: 3Bh) reset value: 0000 0000b, 00h bit allocation Bit Symbol Access 9.5.8.5 PreSet3C register These register bit values must not be changed. ...
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... NXP Semiconductors Table 121. TestDigiSelect register bit descriptions Bit 9.5.8.7 Reserved registers 3Eh, 3Fh These registers are reserved for future use. Table 122. Reserved register (address: 3Eh, 3Fh) reset value: 0000 0000b, 00h bit allocation Bit Symbol Access SLRC400_33 Product data sheet ...
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... NXP Semiconductors 10. SLRC400 command set SLRC400 operation is determined by an internal state machine capable of performing a command set. The commands can be started by writing the command code to the Command register. Arguments and/or data necessary to process a command are mainly exchanged using the FIFO buffer. • ...
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... NXP Semiconductors Table 123. SLRC400 commands overview Command Value Action ReadE2 03h reads data from the EEPROM and sends it to the FIFO buffer. See Remark: Keys cannot be read back LoadConfig 07h reads data from EEPROM and initializes the SLRC400 registers. See ...
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... NXP Semiconductors 10.1.3 Idle command 00h Table 125. Idle command 00h Command Idle The Idle command switches the SLRC400 to its inactive state where it waits for the next command. It does not need or return, any data. The device automatically enters the idle state when a command finishes. When this happens, the SLRC400 sends an interrupt request by setting bit IdleIRq ...
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... NXP Semiconductors 3. Part of the data transmitted to the label is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. While the Transmit command is active, the microprocessor can send further data to the FIFO buffer. This is then appended by the transmitter to the transmitted data stream ...
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... NXP Semiconductors TxLastBits[2:0] FIFOLength[6:0] FIFO empty TxData check FIFO empty accept further data Fig 13. Timing for transmitting byte oriented frames As long as the internal accept further data signal is logic 1, further data can be written to the FIFO buffer. The SLRC400 appends this data to the data stream transmitted using the RF interface ...
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... NXP Semiconductors 10.2.2.2 RF channel redundancy and framing The ISO/IEC 15693 decoder expects the SOF pattern at the beginning of each data stream. When the SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. The ICODE1 decoder however, does not expect an SOF pattern at the start of each data stream, but activates the serial-to-parallel converter when the first data bit is received ...
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... NXP Semiconductors Table 128. Return values for bit-collision positions Collision in bit SOF Least Significant Bit (LSB) of the Least Significant Byte (LSByte) … Most Significant Bit (MSB) of the LSByte LSB of second byte … MSB of second byte LSB of third byte … collision is detected in the SOF, a frame error is flagged and no data is sent to the FIFO buffer ...
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... NXP Semiconductors 10.2.4 States of the label communication The status of the transmitter and receiver state machine can be read from bits ModemState[2:0] in the PrimaryStatus register. The assignment of ModemState[2:0] to the internal action is shown in Table 131. Meaning of ModemState ModemState [2:0] 000 001 010 011 100 ...
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... NXP Semiconductors 10.2.5 Label communication state diagram SOF transmitted data transmitted EOF transmitted and command = Transmit COMMAND REGISTER = IDLE Fig 14. Label communication state diagram SLRC400_33 Product data sheet PUBLIC COMMAND = TRANSMIT, RECEIVE OR TRANSCEIVE IDLE (000) FIFO not empty command = Receive and command = ...
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... NXP Semiconductors 10.3 EEPROM commands 10.3.1 WriteE2 command 01h Table 132. WriteE2 command 01h Command WriteE2 The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM start byte address. Any further bytes are interpreted as data bytes and are programmed into the EEPROM, starting from the given EEPROM start byte address ...
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... NXP Semiconductors 10.3.1.2 Timing diagram Figure 15 NWR write addr addr data byte 0 E2 LSB MSB WriteE2 command active EEPROM programming E2Ready TxIRq Fig 15. EEPROM programming timing diagram Assuming that the SLRC400 finds and reads byte 0 before the microprocessor is able to write byte which takes approximately 2 ...
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... NXP Semiconductors 10.3.2 ReadE2 command 03h Table 133. ReadE2 command 03h Command ReadE2 The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the EEPROM starting byte address. The next byte specifies the number of data bytes returned. When all three argument bytes are available in the FIFO buffer, the specified number of data bytes is copied from the EEPROM into the FIFO buffer, starting from the given EEPROM starting byte address ...
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... NXP Semiconductors 10.4.1.2 Relevant LoadConfig command error flags Valid EEPROM starting byte addresses are between 10h and 60h. 10.4.2 CalcCRC command 12h Table 135. CalcCRC command 12h Command Value Action CalcCRC The CalcCRC command takes all the data from the FIFO buffer as the input bytes for the CRC coprocessor ...
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... NXP Semiconductors When CRCReady and TxIRq flags are set to logic 1 the content of the CRCResultLSB and CRCResultMSB registers and the CRCErr flag are valid. The CRCResultLSB and CRCResultMSB registers hold the content of the CRC, the CRCErr flag indicates CRC validity for the processed data. ...
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... NXP Semiconductors 12.2 Current consumption Table 140. Current consumption Symbol Parameter I digital supply current DDD I analog supply current DDA I TVDD supply current DD(TVDD) 12.3 Pin characteristics 12.3.1 Input pin characteristics Pins D0 to D7, A0, and A1 have TTL input characteristics and behave as defined in Table 141 ...
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... NXP Semiconductors Pin RSTPD has Schmitt trigger CMOS characteristics. In addition internally filtered low-pass filter which causes a propagation delay on the reset signal. Table 143. RSTPD input pin characteristics Symbol Parameter I input leakage current LI V threshold voltage th t propagation delay PD The analog input pin RX has the input capacitance and input voltage range shown in Table 144 ...
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... NXP Semiconductors Table 146. Antenna driver output pin characteristics Symbol Parameter V HIGH-level output voltage LOW-level output voltage output current O 12.4 AC electrical characteristics 12.4.1 Separate read/write strobe bus timing Table 147. Separate read/write strobe timing specification Symbol t LHLL t AVLL t LLAX t LLRWL t SLRWL ...
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... NXP Semiconductors ALE NCS NWR NRD Fig 16. Separate read/write strobe timing diagram Remark: The signal ALE is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care. The multiplexed address and data bus address lines (A0 to A2) must be connected as described in 12 ...
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... NXP Semiconductors Table 148. Common read/write strobe timing specification Symbol t AVDSL t RHAX t DSHDSL t WLDSL ALE NCS R/NW NDS Fig 17. Common read/write strobe timing diagram When separate address and data lines are used, the multiplexed addresses on the data bus do not use the ALE signal. When multiplexed address and data lines are used, the address lines (A0 to A2) must be connected as described in 12 ...
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... NXP Semiconductors Table 149. Common read/write strobe timing specification for EPP Symbol t SLDSL t DSHSH t DSLDV t DSHDZ t DSLQV t DSHQX t DSHWX t DSLDSH t WLDSL t DSL-WAITH t DSH-WAITL Fig 18. Remark: cycle. The timings for the address write and data write cycle are different. In EPP mode, the address lines (A0 to A2) must be connected as described in ...
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... NXP Semiconductors 12.4.4 Clock frequency The clock input is pin OSCIN. Table 150. Clock frequency Symbol f clk δ clk t jit The clock applied to the SLRC400 acts as a time constant for the synchronous system’s encoder and decoder. The stability of the clock frequency is an important factor for ensuring proper performance ...
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... NXP Semiconductors 14. Application information 14.1 Typical application 14.1.1 Circuit diagram Figure 19 SLRC400: control lines MICROPROCESSOR Fig 19. Application example circuit diagram: directly matched antenna 14.1.2 Circuit description The matching circuit consists of an EMC low-pass filter (L0 and C0), matching circuitry (C1 and C2), a receiver circuit (R1, R2, C3 and C4) and the antenna itself. ...
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... NXP Semiconductors Remark: To achieve best performance, all components must be at least equal in quality to those recommended. Remark: The layout has a major influence on the overall performance of the filter. 14.1.2.2 Antenna matching Due to the impedance transformation of the low-pass filter, the antenna coil has to be matched to a given impedance ...
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... NXP Semiconductors • antenna shape factor (K = 1.07 for circular antennas and K = 1.47 for square antennas) • number of turns 1 • natural logarithm function The values of the antenna inductance, resistance, and capacitance at 13.56 MHz depend on various parameters such as: • antenna construction (type of PCB) • ...
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... NXP Semiconductors 14.2.2 Analog test signals The analog test signals can be routed to pin AUX by selecting them using the TestAnaSelect register TestAnaOutSel[4:0] bits. Table 153. Analog test signal selection Value 14.2.3 Digital test signals Digital test signals can be routed to pin SIGOUT by setting bit SignalToSIGOUT = logic 1. ...
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... NXP Semiconductors Table 154. Digital test signal selection TestDigiSignalSel [6:0] C5h 96h 00h If test signals are not used, the TestDigiSelect register address value must be 00h. Remark: All other values for TestDigiSignalSel[6:0] are for production test purposes only. 14.2.4 Examples of analog and digital test signals Figure 20 the Q-clock receiving path ...
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... NXP Semiconductors Fig 20. Q-clock receiving path SLRC400_33 Product data sheet PUBLIC receiving path Q-Clock VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data s_valid All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 23 March 2010 054333 SLRC400 ICODE reader IC 50 μs per division 500 μ ...
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... NXP Semiconductors 15. Package outline SO32: plastic small outline package; 32 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 16. Abbreviations Table 155. Abbreviations and acronyms Acronym ASK BPSK CMOS CRC EOF EPP ETU FIFO HBM IRQ LSB MM MSB NRZ POR PCD PICC RZ SOF SPI TTL 17. References [1] Application note — MIFARE and ICODE1 MICORE Reader IC Family; Directly Matched Antenna Design, document number: 0779xx. ...
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... NXP Semiconductors 18. Revision history Table 156. Revision history Document ID Release date SLRC400_33 20100323 • Modifications: The format of this data sheet has been redesigned to comply with the new identify guidelines of NXP Semiconductors • Legal texts have been adapted to the new company name where appropriate • ...
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... NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 21. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 3. Supported microprocessor and EPP interface signals . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 4. Connection scheme for detecting the parallel interface type . . . . . . . . . . . . . . . . . . . . .7 Table 5. EEPROM memory organization diagram . . . . . .9 Table 6. Product information field byte allocation . . . . . .9 Table 7. Product information field . . . . . . . . . . . . . . . . . .9 Table 8. ...
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... NXP Semiconductors Table 79. DecoderControl register bit descriptions . . . . .52 Table 80. BitPhase register (address: 1Bh) reset value: 0101 0100b, 54h bit allocation . . . . . . .53 Table 81. BitPhase register bit descriptions . . . . . . . . . .53 Table 82. RxThreshold register (address: 1Ch) reset value: 0110 1000b, 68h bit allocation . . . . . . .53 Table 83. RxThreshold register bit descriptions . . . . . . .53 Table 84 ...
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... NXP Semiconductors Table 151. EEPROM characteristics . . . . . . . . . . . . . . . .84 Table 152. Signal routed to pin SIGOUT . . . . . . . . . . . . .87 Table 153. Analog test signal selection . . . . . . . . . . . . . .88 22. Figures Fig 1. SLRC400 block diagram . . . . . . . . . . . . . . . . . . . .3 Fig 2. SLRC400 pin configuration . . . . . . . . . . . . . . . . . .4 Fig 3. Connection to microprocessor: separate read and write strobes . . . . . . . . . . . . . . . . . . . . . .7 Fig 4. Connection to microprocessor: common read and write strobes . . . . . . . . . . . . . . . . . . . . . .8 Fig 5 ...
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... NXP Semiconductors 23. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1.1 Overview of supported microprocessor interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1.2 Automatic microprocessor interface detection . 6 8 ...
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... NXP Semiconductors 9.5.1.2 Command register . . . . . . . . . . . . . . . . . . . . . 40 9.5.1.3 FIFOData register . . . . . . . . . . . . . . . . . . . . . . 41 9.5.1.4 PrimaryStatus register . . . . . . . . . . . . . . . . . . 41 9.5.1.5 FIFOLength register . . . . . . . . . . . . . . . . . . . . 42 9.5.1.6 SecondaryStatus register . . . . . . . . . . . . . . . . 43 9.5.1.7 InterruptEn register . . . . . . . . . . . . . . . . . . . . . 43 9.5.1.8 InterruptRq register 9.5.2 Page 1: Control and status . . . . . . . . . . . . . . . 45 9.5.2.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.5.2.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . 45 9.5.2.3 ErrorFlag register . . . . . . . . . . . . . . . . . . . . . . 45 9.5.2.4 CollPos register . . . . . . . . . . . . . . . . . . . . . . . 46 9.5.2.5 TimerValue register ...
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... NXP Semiconductors 12.3 Pin characteristics . . . . . . . . . . . . . . . . . . . . . 78 12.3.1 Input pin characteristics . . . . . . . . . . . . . . . . . 78 12.3.2 Digital output pin characteristics . . . . . . . . . . . 79 12.3.3 Antenna driver output pin characteristics . . . . 79 12.4 AC electrical characteristics . . . . . . . . . . . . . . 80 12.4.1 Separate read/write strobe bus timing . . . . . . 80 12.4.2 Common read/write strobe bus timing . . . . . . 81 12.4.3 EPP bus timing . . . . . . . . . . . . . . . . . . . . . . . . 82 12.4.4 Clock frequency . . . . . . . . . . . . . . . . . . . . . . . 84 13 EEPROM characteristics ...