MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 105

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
Table 68. PreSet13 register bit descriptions . . . . . . . . . .53
Table 69. PreSet14 register (address: 14h)
Table 70. PreSet14 register bit descriptions . . . . . . . . . .53
Table 71. ModWidth register (address: 15h)
Table 72. ModWidth register bit descriptions . . . . . . . . . .54
Table 73. PreSet16 register (address: 16h)
Table 74. PreSet16 register bit descriptions . . . . . . . . . .54
Table 75. PreSet17 register (address: 17h)
Table 76. PreSet17 register bit descriptions . . . . . . . . . .54
Table 77. RxControl1 register (address: 19h)
Table 78. RxControl1 register bit descriptions . . . . . . . . .55
Table 79. DecoderControl register (address: 1Ah)
Table 80. DecoderControl register bit descriptions . . . . .55
Table 81. BitPhase register (address: 1Bh) reset value:
Table 82. BitPhase register bit descriptions . . . . . . . . . .56
Table 83. RxThreshold register (address: 1Ch)
Table 84. RxThreshold register bit descriptions . . . . . . .56
Table 85. PreSet1D register (address: 1Dh)
Table 86. PreSet1D register bit descriptions . . . . . . . . . .56
Table 87. RxControl2 register (address: 1Eh)
Table 88. RxControl2 register bit descriptions . . . . . . . . .57
Table 89. ClockQControl register (address: 1Fh)
Table 90. ClockQControl register bit descriptions . . . . . .57
Table 91. RxWait register (address: 21h) reset value:
Table 92. RxWait register bit descriptions . . . . . . . . . . . .58
Table 93. ChannelRedundancy register (address: 22h)
Table 94. ChannelRedundancy bit descriptions . . . . . . .58
Table 95. CRCPresetLSB register (address: 23h)
Table 96. CRCPresetLSB register bit descriptions . . . . .59
Table 97. CRCPresetMSB register (address: 24h)
Table 98. CRCPresetMSB bit descriptions . . . . . . . . . . .59
Table 99. PreSet25 register (address: 25h)
Table 100. PreSet25 register bit descriptions . . . . . . . . . .60
Table 101. MFOUTSelect register (address: 26h)
MFRC500_33
Product data sheet
PUBLIC
reset value: 0011 1111b, 3Fh bit allocation . . .53
reset value: 0001 1001b, 19h bit allocation . . .53
reset value: 0001 0011b, 13h bit allocation . . .54
reset value: 0000 0000b, 00h bit allocation . . .54
reset value: 0000 0000b, 00h bit allocation . . .54
reset value: 0111 0011b, 73h bit allocation . . .55
reset value: 0000 1000b, 08h bit allocation . . .55
1010 1101b, ADh bit allocation . . . . . . . . . . . .56
reset value: 1111 1111b, FFh bit allocation . . .56
reset value: 0000 0000b, 00h bit allocation . . .56
reset value: 0100 0001b, 41h bit allocation . . .57
reset value: 000x xxxxb, xxh bit allocation . . . .57
0000 0101b, 06h bit allocation . . . . . . . . . . . . .58
reset value: 0000 0011b, 03h bit allocation . . .58
reset value: 0101 0011b, 63h bit allocation . . .59
reset value: 0101 0011b, 63h bit allocation . . .59
reset value: 0000 0000b, 00h bit allocation . . .59
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 15 March 2010
048033
Table 102. MFOUTSelect register bit descriptions . . . . . 60
Table 103. PreSet27 (address: 27h) reset value:
Table 104. PreSet27 register bit descriptions . . . . . . . . . 60
Table 105. FIFOLevel register (address: 29h)
Table 106. FIFOLevel register bit descriptions . . . . . . . . 61
Table 107. TimerClock register (address: 2Ah)
Table 108. TimerClock register bit descriptions . . . . . . . . 61
Table 109. TimerControl register (address: 2Bh)
Table 110. TimerControl register bit descriptions . . . . . . . 62
Table 111. TimerReload register (address: 2Ch)
Table 112. TimerReload register bit descriptions . . . . . . . 62
Table 113. IRQPinConfig register (address: 2Dh)
Table 114. IRQPinConfig register bit descriptions . . . . . . 63
Table 115. PreSet2E register (address: 2Eh)
Table 116. PreSet2F register (address: 2Fh)
Table 117. Reserved registers (address: 31h, 32h, 33h,
Table 118. Reserved register (address: 39h)
Table 119. TestAnaSelect register (address: 3Ah)
Table 120. TestAnaSelect bit descriptions . . . . . . . . . . . . 64
Table 121. Reserved register (address: 3Bh)
Table 122. Reserved register (address: 3Ch)
Table 123. TestDigiSelect register (address: 3Dh)
Table 124. TestDigiSelect register bit descriptions . . . . . 65
Table 125. Reserved register (address: 3Eh, 3Fh)
Table 126. MFRC500 commands overview . . . . . . . . . . . 66
Table 127. StartUp command 3Fh . . . . . . . . . . . . . . . . . . 68
Table 128. Idle command 00h . . . . . . . . . . . . . . . . . . . . . 68
Table 129. Transmit command 1Ah . . . . . . . . . . . . . . . . . 69
Table 130. Transmission of frames of more than
Table 131. Receive command 16h . . . . . . . . . . . . . . . . . 72
Table 132. Return values for bit-collision positions . . . . . 74
Table 133. Communication error table . . . . . . . . . . . . . . . 75
Table 134. Transceive command 1Eh . . . . . . . . . . . . . . . 75
Highly Integrated ISO/IEC 14443 A Reader IC
reset value: 0000 0000b, 00h bit allocation . . 60
xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 60
reset value: 0000 1000b, 08h bit allocation . . 61
reset value: 0000 0111b, 07h bit allocation . . . 61
reset value: 0000 0110b, 06h bit allocation . . . 62
reset value: 0000 1010b, 0Ah bit allocation . . 62
reset value: 0000 0010b, 02h bit allocation . . 63
reset value: xxxx xxxxb, xxh bit allocation . . . 63
reset value: xxxx xxxxb, xxh bit allocation . . . 63
34h, 35h, 36h, 37h) reset value: xxxx xxxxb,
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63
reset value: xxxx xxxxb, xxh bit allocation . . . 64
reset value: 0000 0000b, 00h bit allocation . . 64
reset value: xxxx xxxxb, xxh bit allocation . . . 65
reset value: xxxx xxxxb, xxh bit allocation . . . 65
reset value: xxxx xxxxb, xxh bit allocation . . . 65
reset value: xxxx xxxxb, xxh bit allocation . . . 66
64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MFRC500
© NXP B.V. 2010. All rights reserved.
continued >>
105 of 110