ATMEGA128A-MN Atmel, ATMEGA128A-MN Datasheet - Page 293
![IC MCU AVR 128K FLASH 64VQFN](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA128A-MN
Manufacturer Part Number
ATMEGA128A-MN
Description
IC MCU AVR 128K FLASH 64VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Core
AVR8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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26.2.1
8151H–AVR–02/11
Latching of Fuses
Table 26-4.
Notes:
Table 26-5.
Notes:
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
The Fuse values are latched when the device enters Programming mode and changes of the
fuse values will have no effect until the part leaves Programming mode. This does not apply to
the EESAVE fuse which will take effect once it is programmed. The fuses are also latched on
power-up in normal mode.
Fuse High
Byte
EESAVE
BOOTSZ1
BOOTSZ0
BOOTRST
Fuse Low
Byte
BODLEVEL
BODEN
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
1. The SPIEN fuse is not accessible in SPI Serial Programming mode.
2. The CKOPT fuse functionality depends on the setting of the CKSEL bits. See
3. The default value of BOOTSZ1:0 results in maximum Boot Size. See
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of lock bits
5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This
1. The default value of SUT1:0 results in maximum start-up time. See
2. The default setting of CKSEL3:0 results in Internal RC Oscillator @ 1MHz. See
Sources” on page 39
and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system
to be running in all sleep modes. This may increase the power consumption.
to avoid static current at the TDO pin in the JTAG interface.
details.
page 39
Fuse High Byte
Fuse Low Byte
Bit No.
Bit No.
3
2
1
0
for details.
5
7
6
4
3
2
1
0
Description
EEPROM memory is preserved
through the Chip Erase
Select Boot Size (see
for details)
Select Boot Size (see
for details)
Select Reset Vector
Description
Brown out detector trigger level
Brown out detector enable
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
for details.
Table 25-6
Table 25-6
Default Value
1 (unprogrammed)
1 (unprogrammed, BOD disabled)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
0 (programmed)
1 (unprogrammed)
Default Value
1 (unprogrammed, EEPROM not
preserved)
0 (programmed)
0 (programmed)
1 (unprogrammed)
ATmega128A
Table 8-9 on page 43
Table 25-6 on page 288
(1)
(2)
(2)
(2)
(3)
(3)
(1)
(2)
“Clock
Table 8-1 on
for
293
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