ATMEGA128A-MN Atmel, ATMEGA128A-MN Datasheet - Page 30
![IC MCU AVR 128K FLASH 64VQFN](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA128A-MN
Manufacturer Part Number
ATMEGA128A-MN
Description
IC MCU AVR 128K FLASH 64VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Core
AVR8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 30 of 386
- Download datasheet (8Mb)
7.6
7.6.1
7.6.2
7.6.3
8151H–AVR–02/11
Register Description
EEARH and EEARL - EEPROM Address Register
EEDR - EEPROM Data Register
EECR - EEPROM Control Register
• Bits 15:12 – Reserved
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bits 11:0 – EEAR[11:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 4
Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096.
The initial value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7:4 – Reserved
These bits are reserved bits in the ATmega128A and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
EEAR7
MSB
R/W
R/W
15
R
X
R
–
7
0
7
0
7
–
0
EEAR6
R/W
R/W
14
R
X
–
6
0
R
6
0
6
–
0
EEAR5
R/W
R/W
13
R
X
–
5
0
R
5
0
5
–
0
EEAR4
R/W
R/W
12
–
4
R
0
X
R
4
–
0
4
0
EEAR11
EEAR3
EERIE
R/W
R/W
R/W
R/W
11
3
X
X
3
0
3
0
EEAR10
EEMWE
EEAR2
R/W
R/W
R/W
R/W
10
X
X
2
0
2
0
2
EEAR9
EEAR1
EEWE
ATmega128A
R/W
R/W
R/W
R/W
1
0
X
1
X
X
9
1
EEAR8
EEAR0
EERE
LSB
R/W
R/W
R/W
R/W
0
0
0
0
8
0
X
X
EEARH
EEARL
EEDR
EECR
30
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