ATMEGA649V-8AUR Atmel, ATMEGA649V-8AUR Datasheet - Page 108
![IC AVR MCU FLASH 64K 1.8V 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA649V-8AUR
Manufacturer Part Number
ATMEGA649V-8AUR
Description
IC AVR MCU FLASH 64K 1.8V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA329-16AU.pdf
(392 pages)
Specifications of ATMEGA649V-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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15.1
15.1.1
108
Register Description
ATmega329/3290/649/6490
GTCCR – General Timer/Counter Control Register
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 15-2. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding pres-
caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and
can be configured to the same value without the risk of one of them advancing during configura-
tion. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware,
and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
Bit
0x23 (0x43)
Read/Write
Initial Value
PSR10
clk
T0
T1
I/O
1. The synchronization logic on the input pins (
Synchronization
Synchronization
TSM
R/W
7
0
ExtClk
6
–
R
0
< f
clk_I/O
R
5
–
0
/2) given a 50/50% duty cycle. Since the edge detector uses
clk
Clear
T1
R
4
–
0
R
T1/T0)
3
–
0
is shown in
R
2
–
0
(1)
PSR2
R/W
1
0
Figure
PSR10
R/W
0
0
15-1.
clk
T0
clk_I/O
GTCCR
2552K–AVR–04/11
/2.5.
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