SPEAR300-2 STMicroelectronics, SPEAR300-2 Datasheet - Page 27

• Manufacturer Part Number: SPEAR300-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR300-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr300
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 56 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 62
• Number Of Timers: 6
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10849-5

SPEAr300
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Cryptographic co-processor (C3)
Main features:
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8-channel ADC
Main features:
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1-bit DAC
The one-bit DAC is a second-order noise shaper based on the TDM hardware. The action
memory determines whether a new sample needs to be sent to the DAC during the next
byte. Samples are read from the buffer memory.
Supported cryptographic algorithms:
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Instruction driven DMA based programmable engine.
AHB master port for data access from/to system memory.
AHB slave port for co-processor register accesses and initial engine-setup
The co-processor is fully autonomous (DMA input reading, cryptographic operation
execution, DMA output writing) after being set up by the host processor
The co-processor executes programs written by the host in memory, it can execute an
unlimited list of programs.
The co-processor supports hardware chaining of cryptographic blocks for optimized
execution of data-flow requiring multiple algorithms processing over the same set of
data (for example encryption + hashing on the fly)
Successive approximation conversion method
10-bit resolution @1 Msps
Hardware supporting up to 13.5 bits resolution at 8 ksps by oversampling and
accumulation
Eight analog input (AIN) channels, ranging from 0 to 2.5 V
INL ± 1 LSB, DNL ± 1 LSB
Programmable conversion speed, (min. conversion time is 1 s)
Programmable average results from 1 (no averaging) up to 128
Programmable auto scan for all the eight channels.
Normal or enhanced mode;
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Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes
Data encryption standard (DES) cipher in ECB and CBC modes.
SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests.
In normal mode the conversion start upon CPU request
In enhanced mode the ADC converts continuously the selected channels inserting
a selectable amount of time between two conversions.
Doc ID 16324 Rev 2
Architecture overview
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