WM8776SEFT/V Wolfson Microelectronics, WM8776SEFT/V Datasheet - Page 18

• Manufacturer Part Number: WM8776SEFT/V
• Description: Audio CODECs Stereo CODEC with 5-Ch Mux
• Manufacturer: Wolfson Microelectronics

Specifications of WM8776SEFT/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8776
ZERO DETECT
POWERDOWN MODES
w
Table 8 shows the settings for ADCRATE and DACRATE for common sample rates and
ADCMCLK/DACMCLK frequencies.
Table 8 Master Mode ADC/DACLRC Frequency Selection
ADCBCLK and DACBCLK are also generated by the WM8776. The frequency of ADCBCLK and
DACBCLK depends on the mode of operation.
In 128/192fs modes (DACRATE=000 or 001) BCLK = MCLK/2. In 256/384/512fs modes
(ADCRATE/DACRATE=010 or 011 or 100) BCLK = MCLK/4. However if DSP mode is selected as
the audio interface mode then BCLK=MCLK. Note that DSP mode cannot be used in 128fs mode for
word lengths greater than 16 bits or in 192fs mode for word lengths greater than 24 bits.
The WM8776 has a zero detect circuit for each DAC channel, which detects when 1024 consecutive
zero samples have been input. The two zero flag outputs (ZFLAGL and ZFLAGR) may be
programmed to output the zero detect signals (see Table 9) that may then be used to control external
muting circuits. A ‘1’ on ZFLAGL or ZFLAGR indicates a zero detect. The zero detect may also be
used to automatically enable the PGA mute by setting IZD. The zero flag output may be disabled by
setting DZFM to 00. The zero flag signal for each DAC channel will only be enabled if it is enabled as
an input to the output summing stage.
The WM8776 has powerdown control bits allowing specific parts of the WM8776 to be powered off
when not being used. The 5-channel input source selector and input buffer may be powered down
using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN5L/R)
are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input
PGAs. The stereo DAC has a separate powerdown control bit, DACPD allowing the DAC and
analogue output mixer to be powered off when not in use. This also switches the analogue outputs
VOUTL/R to VMIDDAC to maintain a dc level on the output.
Setting AINPD, ADCPD and DACPD will powerdown everything except the references VMIDADC,
ADCREF and VMIDDAC. These may be powered down by setting PDWN. Setting PDWN will
override all other powerdown control bits. It is recommended that AINPD, HPPD, ADCPD and
DACPD are set before setting PDWN. The default is for all blocks to be enabled other than HPPD.
DZFM[1:0]
Table 9 Zero Flag Output Select
SAMPLING
(DACLRC/
ADCLRC)
44.1kHz
192kHz
32kHz
48kHz
96kHz
00
01
10
11
RATE
Zero flag disabled
Left channel zero
Both channel zero
Either channels zero
DACRATE
5.6448
12.288
24.576
4.096
6.144
128fs
=000
ZFLAGL
DACRATE
18.432
36.864
6.144
8.467
9.216
192fs
=001
Zero flag disabled
Right channel zero
Both channel zero
Either channel zero
System Clock Frequency (MHz)
ZFLAGR
Unavailable Unavailable Unavailable Unavailable
ADCRATE/
DACRATE
11.2896
12.288
24.576
8.192
256fs
=010
ADCRATE/
DACRATE
16.9340
12.288
18.432
36.864
384fs
=011
PD, Rev 4.1, September 2008
Unavailable Unavailable
ADCRATE/
DACRATE
22.5792
16.384
24.576
512fs
=100
Production Data
ADCRATE/
DACRATE
33.8688
24.576
36.864
768fs
=101
18