WM8776SEFT/V Wolfson Microelectronics, WM8776SEFT/V Datasheet - Page 25

• Manufacturer Part Number: WM8776SEFT/V
• Description: Audio CODECs Stereo CODEC with 5-Ch Mux
• Manufacturer: Wolfson Microelectronics

Specifications of WM8776SEFT/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
CONTROL INTERFACE REGISTERS
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DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits:
In left justified, right justified or I
ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the
opposite of that shown Figure 13, Figure 14, etc. Note that if this feature is used as a means of
swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes,
the LRP register bit is used to select between early and late modes.
By default, ADCLRC, DACLRC and DIN are sampled on the rising edge of ADCBCLK and DACBCLK
and should ideally change on the falling edge. Data sources that change ADCLRC/DACLRC and DIN
on the rising edge of ADCBCLK/DACBCLK can be supported by setting the BCP register bit. Setting
BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 13, Figure 14, etc.
The WL[1:0] bits are used to control the input word length.
Note: If 32-bit mode is selected in right justified mode, the WM8776 defaults to 24 bits.
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8776 pads the unused LSBs with zeros. If
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.
Note: In 24 bit I
high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
DAC Interface Control
ADC Interface Control
DAC Interface Control
ADC Interface Control
DAC Interface Control
ADC Interface Control
DAC Interface Control
ADC Interface Control
R10 (0Ah)
R11 (0Bh)
R10 (0Ah)
R11 (0Bh)
R10 (0Ah)
R11 (0Bh)
R10 (0Ah)
R11 (0Bh)
0001010
0001011
0001010
0001011
0001010
0001011
0001010
0001011
2
S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is
BIT
1:0
1:0
BIT
BIT
BIT
5:4
5:4
2
2
3
3
DACFMT
ADCFMT
DACBCP
ADCBCP
DACLRP
ADCLRP
DACWL
ADCWL
LABEL
LABEL
LABEL
LABEL
[1:0]
[1:0]
[1:0]
[1:0]
2
S modes, the LRP register bit controls the polarity of
DEFAULT
DEFAULT
DEFAULT
DEFAULT
0
0
10
10
10
10
0
0
In left/right/ I
ADCLRC/DACLRC Polarity (normal)
In DSP mode:
Interface format Select
BCLK Polarity (DSP modes)
Word Length
0 : normal ADCLRC/DACLRC
polarity
1: inverted ADCLRC/DACLRC
polarity
0 : Early DSP mode
1: Late DSP mode
00 : right justified mode
01: left justified mode
10: I
11: DSP (early or late) mode
0 : normal BCLK polarity
1: inverted BCLK polarity
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
PD, Rev 4.1, September 2008
2
DESCRIPTION
S mode
DESCRIPTION
DESCRIPTION
DESCRIPTION
2
S modes:
WM8776
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