WM8776SEFT/V Wolfson Microelectronics, WM8776SEFT/V Datasheet - Page 37

• Manufacturer Part Number: WM8776SEFT/V
• Description: Audio CODECs Stereo CODEC with 5-Ch Mux
• Manufacturer: Wolfson Microelectronics

Specifications of WM8776SEFT/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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MAXIMUM GAIN (ALC ONLY) AND MAXIMUM ATTENUATION
To prevent low level signals being amplified too much by the ALC, the MAXGAIN register sets the
upper limit for the gain. This prevents low level noise being over-amplified. The MAXGAIN register
has no effect on the limiter operation.
The MAXATTEN register has different operation for the limiter and for the ALC. For the limiter it
defines the maximum attenuation below the static (user programmed) gain. For the ALC, it defines
the lower limit for the gain.
HOLD TIME (ALC ONLY)
The ALC also has a hold time, which is the time delay between the peak level detected being below
target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2
2.67ms, 5.33ms, 10.67ms etc. up to 43.7ms. Alternatively, the hold time can also be set to zero. The
hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the
signal level is above target.
OVERLOAD DETECTOR (ALC ONLY)
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes an
overload detector. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is
ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
(Note: If ATK = 0000, then the overload detector makes no difference to the operation of the ALC. It
is designed to prevent clipping when long attack times are used).
Limiter Control
ALC Control 1
ALC Control 2
REGISTER
REGISTER
ADDRESS
ADDRESS
R16 (10h)
R20 (14h)
R17 (11h)
0010000
0010100
0010001
BIT
BIT
6:4
3:0
3:0
MAXATTEN
MAXGAIN
HLD[3:0]
LABEL
LABEL
DEFAULT
DEFAULT
(+24dB)
0110
0000
111
Set maximum gain for the PGA (ALC
only)
111 : +24dB
110 : +20dB
…..(-4dB steps)
010 : +4dB
001 : 0dB
000 : 0dB
Maximum attenuation of PGA
Limiter
(attenuation
below static)
0011 or lower:
-3dB
0100: -4dB
…. (-1dB steps)
1100 or higher:
-12dB
ALC hold time before gain is
increased.
0000: 0ms
0001: 2.67ms
0010: 5.33ms
… (time doubles with every step)
1111: 43.691s
DESCRIPTION
DESCRIPTION
PD, Rev 4.1, September 2008
ALC (lower PGA
gain limit)
1010 or lower:
-1dB
1011 : -5dB
….. (-4dB steps)
1110 : -17dB
1111 : -21dB
WM8776
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) steps, e.g.
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