A3P250L-VQG100 Actel, A3P250L-VQG100 Datasheet - Page 124

• Manufacturer Part Number: A3P250L-VQG100
• Description: FPGA - Field Programmable Gate Array 2.5K SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P250L-VQG100

• Processor Series: A3P250
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 68
• Data Ram Size: 36864
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 250 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3L DC and Switching Characteristics
Figure 2-32 • Input DDR Timing Diagram
Table 2-189 • Input DDR Propagation Delays
2- 11 0
Out_QR
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD1
DDRISUD2
DDRIHD1
DDRIHD2
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage supply levels, refer to
Timing Characteristics
Commercial-Case Conditions: T
1.5 V DC Core Voltage
t
t
1
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (fall)
Data Setup for Input DDR (rise)
Data Hold for Input DDR (fall)
Data Hold for Input DDR (rise)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
DDRICLR2Q1
DDRICLR2Q2
t
DDRIREMCLR
2
3
t
DDRICLKQ1
J
Description
= 70°C, Worst-Case VCC = 1.425 V
4
2
R e visio n 9
3
5
t
DDRICLKQ2
t
DDRISUD
Table 2-6 on page 2-7
6
4
5
7
t
DDRIHD
0.28
0.40
0.29
0.25
0.00
0.00
0.47
0.58
0.00
0.23
0.18
0.31
0.28
–1
t
for derating values.
8
DDRIRECCLR
6
7
0.33
0.47
0.34
0.29
0.00
0.00
0.55
0.68
0.00
0.27
0.22
0.36
0.32
Std.
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns