A3P250L-VQG100 Actel, A3P250L-VQG100 Datasheet - Page 158
A3P250L-VQG100
Manufacturer Part Number
A3P250L-VQG100
Description
FPGA - Field Programmable Gate Array 2.5K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P250L-VQG100
Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
68
Data Ram Size
36864
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P250L-VQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P250L-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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ProASIC3L DC and Switching Characteristics
JTAG 1532 Characteristics
2- 14 4
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the
Characteristics" section on page 2-18
Timing Characteristics
Table 2-216 • JTAG 1532 – Applies to 1.5 V DC Core Voltage
Table 2-217 • JTAG 1532 – Applies to 1.2 V DC Core Voltage
Parameter
t
t
t
t
t
t
F
t
t
t
Note:
Parameter
t
t
t
t
t
t
F
t
t
t
Note:
DISU
DIHD
TMSSU
TMDHD
TCK2Q
RSTB2Q
TRSTREM
TRSTREC
TRSTMPW
DISU
DIHD
TMSSU
TMDHD
TCK2Q
RSTB2Q
TRSTREM
TRSTREC
TRSTMPW
TCKMAX
TCKMAX
For specific junction temperature and voltage supply levels, refer to
derating values.
For specific junction temperature and voltage supply levels, refer to
derating values.
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
Reset to Q (data out)
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
Reset to Q (data out)
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
for more details.
Description
Description
R e visio n 9
J
J
= 70°C, Worst-Case VCC = 1.425 V
= 70°C, Worst-Case VCC = 1.14 V
22.67
24.00
25.00
20.00
0.57
1.13
0.57
1.13
5.67
0.00
0.23
TBD
0.75
1.50
0.75
1.50
6.00
0.45
0.00
TBD
–1
–1
Table 2-6 on page 2-7
Table 2-6 on page 2-7
26.67
21.00
29.41
17.00
TBD
TBD
Std.
0.67
1.33
0.67
1.33
6.67
0.00
0.27
Std.
0.88
1.76
0.88
1.76
7.06
0.53
0.00
"User I/O
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
for
for
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