A3P250-VQG100 Actel, A3P250-VQG100 Datasheet

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A3P250-VQG100

Manufacturer Part Number
A3P250-VQG100
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet

Specifications of A3P250-VQG100

Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
157
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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October 2009
© 2010 Actel Corporation
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
High Capacity
Reprogrammable Flash Technology
High Performance
In-System Programming (ISP) and Security
Low Power
High-Performance Routing Hierarchy
Advanced I/O
Table 1 • ProASIC3 Product Family
ProASIC3 Devices
Cortex-M1 Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits
Secure (AES) ISP 2
Integrated PLL in CCCs
VersaNet Globals 3
I/O Banks
Maximum User I/Os
Package Pins
Notes:
1. Refer to the
2. AES is not available for Cortex-M1 ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the
5. The M1A3P250 device does not support this package.
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• FlashLock
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
• Segmented, Hierarchical Routing and Clock Structure
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
QFN
CS
VQFP
TQFP
PQFP
FBGA
† A3P015 and A3P030 devices do not support this feature.
Process
Standard (AES) Decryption (except ARM
devices) via JTAG (IEEE 1532–compliant)
®
Cortex-M1
to Secure FPGA Contents
1
product brief for more information.
A3P015
15,000
QN68
128
384
49
1
6
2
QN48, QN68,
®
-enabled ProASIC
A3P030
30,000
QN132
VQ100
256
768
81
1
6
2
A3P060
QN132
VQ100
60,000
CS121
TQ144
FG144
1,536
512
Yes
18
18
96
4
1
1
2
®
3
‡ Supported only by A3P015 and A3P030 devices.
ProASIC3E Flash Family FPGAs
A3P125
125,000
Clock Conditioning Circuit (CCC) and PLL
Embedded Memory
ARM Processor Support in ProASIC3 FPGAs
QN132
VQ100
TQ144
PQ208
FG144
1,024
3,072
133
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B,
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
• True Dual-Port SRAM (except ×18)
• M1 ProASIC3 Devices—ARM
Yes
36
18
8
1
1
2
Allowing I/Os to Operate from 2.7 V to 3.6 V
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X
2.5 V / 5.0 V Input
M-LVDS (A3P250 and above)
and External Feedback
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
Available with or without Debug
FG144/256
M1A3P250
QN132
A3P250
250,000
VQ100
PQ208
2,048
6,144
Yes
157
36
18
8
1
1
4
5
I/O
5
FG144/256/
M1A3P400
Standards:
A3P400
400,000
PQ208
9,216
Yes
194
484
54
12
18
1
1
4
datasheet.
®
Cortex™-M1 Soft Processor
and Drive Strength
LVTTL,
FG144/256/
M1A3P600
A3P600
600,000
13,824
PQ208
108
Yes
235
484
24
18
1
1
4
LVCMOS
Revision 9
and LVCMOS
M1A3P1000
FG144/256/
1,000,000
A3P1000
PQ208
24,576
144
Yes
300
484
32
18
1
1
4
3.3 V /
®
I

A3P250-VQG100 Summary of contents

Page 1

... Six chip (main) and three quadrant global networks are available for A3P060 and above. 4. For higher densities and support of additional features, refer to the 5. The M1A3P250 device does not support this package. † A3P015 and A3P030 devices do not support this feature. October 2009 © ...

Page 2

... Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to the ProASIC3 FPGA Fabric User’s Guide 4. FG256 and FG484 are footprint-compatible packages. 5. " ...

Page 3

... Part Number ProASIC3 Devices A3P015 = 15,000 System Gates A3P030 = 30,000 System Gates A3P060 = 60,000 System Gates A3P125 = 125,000 System Gates A3P250 = 250,000 System Gates A3P400 = 400,000 System Gates A3P600 = 600,000 System Gates A3P1000 = 1,000,000 System Gates ProASIC3 Devices with Cortex-M1 M1A3P250 = ...

Page 4

... References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. A3P015 and A3P030 The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features A3P060 A3P125 A3P250 M1A3P250 – – – – – – ...

Page 5

... CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 ProASIC3 Flash Family FPGAs ...

Page 6

...

Page 7

... ProASIC3 Device Family Overview General Description ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASIC advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools ...

Page 8

... This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based ProASIC3 devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The ...

Page 9

Advanced Flash Technology The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of ...

Page 10

... Decryption FlashROM Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000) The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable latch by programming the appropriate flash switch interconnections ...

Page 11

... Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents ...

Page 12

ProASIC3 Device Family Overview In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are ...

Page 13

... Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS. B-LVDS and M-LVDS can support loads. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system ...

Page 14

...

Page 15

ProASIC3 DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the ...

Page 16

... To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel’s timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O ...

Page 17

... JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The V CC for more details) ...

Page 18

ProASIC3 DC and Switching Characteristics Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation VCC = VCCI + VT where VT can be from 0. 0.9 V (typically ...

Page 19

... Device Pin Count Still Air 200 ft./min. jc A3P030 132 0.4 21.4 A3P060 132 0.3 21.2 A3P125 132 0.2 21.1 A3P250 132 0.1 21.0 All devices 100 10.0 35.3 All devices 144 11.0 33.5 All devices 208 8.0 26.1 All devices 208 3 ...

Page 20

... All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification 70° 1.425 Junction Temperature (°C) –40°C 0°C 25°C 0.88 0.93 0.95 0.83 0.88 0.90 0.80 0.84 0.87 A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Table 2-11 and Table 2-12 on page Static Power VMV ( ...

Page 21

Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 ...

Page 22

ProASIC3 DC and Switching Characteristics Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 4 3.3 V LVCMOS Wide Range ...

Page 23

Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard I/O Banks C Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 4 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 ...

Page 24

... P Dynamic contribution for PLL AC13 Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator or SmartPower tool in Libero 2- 10 Device Specific Dynamic Contributions (µW/MHz) 14.50 12.80 12.80 11.00 11.00 9.30 9.30 9.30 2 ...

Page 25

... I/O output pin static power (standard-dependent) DC3 P Static PLL contribution DC4 P Bank quiescent power (V DC5 Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel Device Specific Static Power (mW) See See -dependent) CCI ProASIC3 Flash Family FPGAs See Table 2-7 on page 2-6 ...

Page 26

... ProASIC3 DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: • ...

Page 27

Combinatorial Cells Contribution—P α C-CELL C-CELL the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in ...

Page 28

ProASIC3 DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means ...

Page 29

User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D Q (Applicable to Advanced I/O Banks only 0.24 ns ICLKQ t = 0.26 ns ISUD Input LVTTL Clock Register Cell t = 0.76 ...

Page 30

ProASIC3 DC and Switching Characteristics t PY PAD DIN V PAD Y GND DIN GND Figure 2-3 • Input Buffer Timing Model and Delays (example CLK I/O Interface = MAX(t (R), t (F)) ...

Page 31

DOUT D Q CLK D From Array I/O Interface D DOUT PAD Figure 2-4 • Output Buffer Model and Delays (example DOUT t = MAX(t (R MAX(t DOUT DOUT t t DOUT ...

Page 32

ProASIC3 DC and Switching Characteristics t EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD Vtrip D 50 EOUT (R) 50% EOUT t ZLS PAD ...

Page 33

Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to ...

Page 34

ProASIC3 DC and Switching Characteristics Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard Plus I/O Banks Equiv. Software Default Drive Drive Strength 2 I/O ...

Page 35

Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard I/O Banks Equiv. Softwar e Default Drive Drive Strength Slew 2 I/O Standard Strength Option Rate ...

Page 36

ProASIC3 DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-22 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 ...

Page 37

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: T Worst-Case V (per standard) CCI Advanced I/O Banks I/O Standard 3.3 V LVTTL / High 35 3.3 V LVCMOS 3.3 ...

Page 38

ProASIC3 DC and Switching Characteristics Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: T VCCI (per standard) Standard Plus I/O Banks I/O Standard 3.3 V LVTTL / 3.3 V ...

Page 39

Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: T Worst-Case V (per standard) CCI Standard I/O Banks I/O Standard 3.3 V LVTTL / High 3.3 V LVCMOS 3.3 V ...

Page 40

... V LVCMOS 3.3 V PCI/PCI-X Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on V considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx (PULL-DOWN-MAX (VCCImax – V (PULL-UP-MAX) 4 ...

Page 41

... These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend drive strength selection, temperature, and process. For board design CCI considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx (VOLspec (PULL-DOWN-MAX) OLspec (VCCImax – ...

Page 42

... V LVCMOS 1.5 V LVCMOS Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on V considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx (PULL-DOWN-MAX (VCCImax – V (PULL-UP-MAX) 4 ...

Page 43

Table 2-32 • I/O Short Currents I /I OSH Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X Notes: ...

Page 44

ProASIC3 DC and Switching Characteristics Table 2-33 • I/O Short Currents I Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 ...

Page 45

... The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals ...

Page 46

ProASIC3 DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-37 ...

Page 47

Table 2-39 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS V IL Min. Max. Min. Drive Strength –0.3 0 –0.3 0.8 ...

Page 48

ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT 4 mA Std. 0.66 7.66 –1 ...

Page 49

Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.66 10.26 –1 0.56 8.72 –2 0.49 7.66 6 ...

Page 50

ProASIC3 DC and Switching Characteristics Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT 4 mA Std. 0.66 7.20 –1 0.56 ...

Page 51

Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.66 9.68 –1 0.56 8.23 –2 0.49 7.23 ...

Page 52

ProASIC3 DC and Switching Characteristics Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t DOUT 2 mA Std. 0.66 –1 0.56 –2 0.49 4 ...

Page 53

V LVCMOS Wide Range Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V Equiv. LVCMOS Software Wide Range Default VIL Drive Drive Strength Min. Max. 1 Strength Option V V ...

Page 54

ProASIC3 DC and Switching Characteristics Table 2-49 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V Equiv. LVCMOS Software Wide Range Default V IL Drive Drive Strength Min. Max. 1 Strength Option V ...

Page 55

Timing Characteristics Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Equiv. Software Default Drive Drive Strength Speed 1 Strength Option Grade t DOUT 100 µ Std. ...

Page 56

ProASIC3 DC and Switching Characteristics Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Equiv. Software Default Drive Drive Strength Speed 1 Strength Option Grade 100 µ ...

Page 57

Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Equiv. Software Default Drive Drive Strength Speed 1 Strength Option Grade t DOUT 100 µ Std. 0.60 ...

Page 58

ProASIC3 DC and Switching Characteristics Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Equiv. Software Default Drive Drive Strength Speed 1 Strength Option Grade 100 µA 2 ...

Page 59

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew Commercial-Case Conditions 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Equiv. Software Default Drive Drive Strength Speed 1 ...

Page 60

ProASIC3 DC and Switching Characteristics Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Equiv. Software Default Drive Drive Strength Speed 1 Strength Option Grade 100 µ ...

Page 61

V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-56 • Minimum and Maximum ...

Page 62

ProASIC3 DC and Switching Characteristics Table 2-58 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 2.5 V LVCMOS VIL Min. Max., Drive Strength –0.3 0 –0.3 0.7 6 ...

Page 63

Timing Characteristics Table 2-60 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.60 8.66 –1 0.51 7.37 –2 0.45 6. Std. ...

Page 64

ProASIC3 DC and Switching Characteristics Table 2-61 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.60 11.40 –1 0.51 9.69 –2 0.45 8.51 ...

Page 65

Table 2-62 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.66 8.28 –1 0.56 7.04 –2 0.49 6. Std. 0.66 ...

Page 66

ProASIC3 DC and Switching Characteristics Table 2-64 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t DOUT 2 mA Std. 0.66 –1 0.56 –2 0. Std. 0.66 –1 ...

Page 67

V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-66 • Minimum and ...

Page 68

ProASIC3 DC and Switching Characteristics Table 2-68 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.8 V LVCMOS VIL Drive Min. Max. Strength –0.3 0.35 * VCCI 4 mA –0.3 ...

Page 69

Timing Characteristics Table 2-70 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.66 11.86 –1 0.56 10.09 –2 0.49 8. Std. ...

Page 70

ProASIC3 DC and Switching Characteristics Table 2-71 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.66 15.53 –1 0.56 13.21 –2 0.49 11.60 ...

Page 71

Table 2-72 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.66 11.33 –1 0.56 9.64 –2 0.49 8. Std. 0.66 ...

Page 72

ProASIC3 DC and Switching Characteristics Table 2-73 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t DOUT 2 mA Std. 0.66 14.80 –1 0.56 12.59 –2 0.49 11.05 4 ...

Page 73

Table 2-75 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. 0.66 15.01 –1 0.56 12.77 –2 0.49 11. Std. 0.66 10.10 –1 ...

Page 74

ProASIC3 DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output ...

Page 75

Table 2-78 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.5 V LVCMOS VIL Drive Min. Max. Min. Strength –0.3 0.35 * VCCI 0.65 * VCCI Notes ...

Page 76

ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-80 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t DOUT 2 mA Std. 0.66 8.36 –1 0.56 7.11 –2 0.49 6.24 ...

Page 77

Table 2-81 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.66 12.78 –1 0.56 10.87 –2 0.49 9. Std. 0.66 10.01 ...

Page 78

ProASIC3 DC and Switching Characteristics Table 2-82 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t DOUT 2 mA Std. 0.66 –1 0.56 –2 0. Std. 0.66 ...

Page 79

Table 2-85 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Standard I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. 0.66 12.33 –1 0.56 10.49 –2 0.49 9.21 Note: For specific junction temperature and ...

Page 80

... Per PCI specification Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described VCCI for ...

Page 81

... Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards ...

Page 82

ProASIC3 DC and Switching Characteristics Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels DC Parameter VCCI Supply Voltage VOL Output Low Voltage VOH Output High Voltage 4 I Output Lower Current Output High ...

Page 83

... These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in ...

Page 84

ProASIC3 DC and Switching Characteristics LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. ...

Page 85

I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset PRE Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-14 • ...

Page 86

ProASIC3 DC and Switching Characteristics Table 2-96 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...

Page 87

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-15 • Timing Model of ...

Page 88

ProASIC3 DC and Switching Characteristics Table 2-97 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...

Page 89

Input Register 50% 50% CLK t ISUD 1 50% Data Enable 50% t IHE t ISUE Preset Clear Out_1 Figure 2-16 • Input Register Timing Diagram Timing Characteristics Table 2-98 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter ...

Page 90

ProASIC3 DC and Switching Characteristics Output Register 50% CLK 50% 1 Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-17 • Output Register Timing Diagram Timing Characteristics Table 2-99 • Output Data Register Propagation Delays Commercial-Case Conditions: ...

Page 91

Output Enable Register 50% 50% CLK t OESUD 50% 1 D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT t Figure 2-18 • Output Enable Register Timing Diagram 50% 50% t OEHD 50 OEWPRE t OERECPRE 50% ...

Page 92

ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-100 • Output Enable Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable Register OESUD t Data Hold ...

Page 93

DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-19 • Input DDR Timing Model Table 2-101 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...

Page 94

ProASIC3 DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-20 • Input DDR Timing Diagram Timing Characteristics Table 2-102 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out ...

Page 95

Output DDR Module A Data_F (from core) B CLK CLKBUF C D Data_R (from core) B CLR INBUF C Figure 2-21 • Output DDR Timing Model Table 2-103 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out DDROCLKQ t Asynchronous ...

Page 96

ProASIC3 DC and Switching Characteristics CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-22 • Output DDR Timing Diagram Timing Characteristics Table 2-104 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter ...

Page 97

VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the and ProASIC3/E Macro ...

Page 98

ProASIC3 DC and Switching Characteristics OUT GND VCC OUT Figure 2-24 • Timing Model and Waveforms NAND2 or Any Combinatorial Logic MAX(t PD PD(RR) where edges are applicable for ...

Page 99

Timing Characteristics Table 2-105 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell Equation INV AND2 · B NAND2 Y = !(A · B) OR2 NOR2 Y = ...

Page 100

ProASIC3 DC and Switching Characteristics 50% CLK 50% Data EN 50 PRE SUE CLR Out Figure 2-26 • Timing Model and Waveforms Timing Characteristics Table 2-106 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the ...

Page 101

... CCC Figure 2-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing Figure 2- example of a global tree used for clock routing. The is driven by a CCC located on the west side of the A3P250 device ProASIC3 Flash Family FPGAs Central Global Rib ...

Page 102

ProASIC3 DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the ...

Page 103

Table 2-109 • A3P060 Global Resource Commercial-Case Conditions: T Parameter Description t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH t Minimum Pulse Width ...

Page 104

... ProASIC3 DC and Switching Characteristics Table 2-111 • A3P250 Global Resource Commercial-Case Conditions: T Parameter Description t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH t Minimum Pulse Width Low for Global Clock ...

Page 105

Table 2-113 • A3P600 Global Resource Commercial-Case Conditions: T Parameter Description t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH t Minimum Pulse Width ...

Page 106

... MHz to 350 MHz Acquisition Time (A3P250 and A3P1000 only) (all other dies) 5 Tracking Jitter (A3P250 and A3P1000 only) (all other dies) Output Duty Cycle Delay Range in Block: Programmable Delay 1 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay Notes: 1. Maximum value obtained for a – ...

Page 107

Output Signal Note: Peak-to-peak jitter measurements are defined by T Figure 2-28 • Peak-to-Peak Jitter Definition ProASIC3 Flash Family FPGAs T T period_max period_min = T – T peak-to-peak period_max period_min ...

Page 108

ProASIC3 DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-29 • RAM Models 2- 94 RAM4K9 RADDR8 ADDRA11 DOUTA8 RADDR7 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA REN ...

Page 109

Timing Waveforms t CYC t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-30 • RAM Read for Pass-Through Output t CYC t CKH CLK ...

Page 110

ProASIC3 DC and Switching Characteristics CLK t AS ADD t BKS BLK_B t ENS WEN_B Figure 2-32 • RAM Write, Output Retained (WMODE = 0) CLK ADD BLK_B WEN_B (pass-through) DO (pipelined) Figure 2-33 ...

Page 111

CLK1 ADD1 DI1 1 t CCKH CLK2 WEN_B1 WEN_B2 A ADD2 0 DI2 D 0 DO2 D n (pass-through) DO2 D (pipelined) n Figure 2-34 • Write Access after ...

Page 112

ProASIC3 DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DO2 (pass-through) DO2 (pipelined) Figure 2-35 • Read Access after Write onto Same Address ...

Page 113

CLK1 ADD1 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 DI2 1 WEN_B2 Figure 2-36 • Write Access after Read onto Same Address t ...

Page 114

ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-116 • RAM4K9 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t BLK_B setup ...

Page 115

Table 2-117 • RAM512X18 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup time DS t Input data ...

Page 116

ProASIC3 DC and Switching Characteristics FIFO Figure 2-38 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 ...

Page 117

Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-39 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-40 • FIFO EMPTY Flag and AEMPTY Flag Assertion t ...

Page 118

ProASIC3 DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-41 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (Address Counter) (EMPTY) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY ...

Page 119

... Timing Characteristics Table 2-118 • FIFO (for all dies except A3P250) Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS t Input Data (DI) Hold Time ...

Page 120

... ProASIC3 DC and Switching Characteristics Table 2-119 • FIFO (for A3P250 only, aspect-ratio-dependent) Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS t Input Data (DI) Hold Time ...

Page 121

... Table 2-120 • A3P250 FIFO 512×8 Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS t Input Data (DI) Hold Time DH t Clock High to New Data Valid on DO (flow-through) ...

Page 122

... ProASIC3 DC and Switching Characteristics Table 2-121 • A3P250 FIFO 1k×4 Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS t Input Data (DI) Hold Time ...

Page 123

... Table 2-122 • A3P250 FIFO 2k×2 Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS t Input Data (DI) Hold Time DH t Clock High to New Data Valid on DO (flow-through) ...

Page 124

... ProASIC3 DC and Switching Characteristics Table 2-123 • A3P250 FIFO 4k×1 Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS t Input Data (DI) Hold Time ...

Page 125

Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-44 • Timing Diagram Timing Characteristics Table 2-124 • Embedded FlashROM Access Time Parameter Description t Address Setup Time SU t Address Hold Time HOLD t Clock ...

Page 126

... Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. ...

Page 127

... Package Pin Assignments 48-Pin QFN Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC3 Flash Family FPGAs Pin ...

Page 128

Package Pin Assignments 48-Pin QFN Pin Number A3P030 Function 1 IO82RSB1 2 GEC0/IO73RSB1 3 GEA0/IO72RSB1 4 GEB0/IO71RSB1 5 GND 6 VCCIB1 7 IO68RSB1 8 IO67RSB1 9 IO66RSB1 10 IO65RSB1 11 IO64RSB1 12 IO62RSB1 13 IO61RSB1 14 IO60RSB1 15 IO57RSB1 16 ...

Page 129

... QFN Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC3 Flash Family FPGAs Pin A1 Mark ...

Page 130

Package Pin Assignments 68-Pin QFN Pin Number A3P015 Function 1 IO82RSB1 2 IO80RSB1 3 IO78RSB1 4 IO76RSB1 5 GEC0/IO73RSB1 6 GEA0/IO72RSB1 7 GEB0/IO71RSB1 8 VCC 9 GND 10 VCCIB1 11 IO68RSB1 12 IO67RSB1 13 IO66RSB1 14 IO65RSB1 15 IO64RSB1 16 ...

Page 131

QFN Pin Number A3P030 Function 1 IO82RSB1 2 IO80RSB1 3 IO78RSB1 4 IO76RSB1 5 GEC0/IO73RSB1 6 GEA0/IO72RSB1 7 GEB0/IO71RSB1 8 VCC 9 GND 10 VCCIB1 11 IO68RSB1 12 IO67RSB1 13 IO66RSB1 14 IO65RSB1 15 IO64RSB1 16 IO63RSB1 17 IO62RSB1 ...

Page 132

... C21 B23 A25 D3 Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx A37 A48 B34 B44 C31 C40 C20 C11 ...

Page 133

QFN Pin Number A3P030 Function A1 IO01RSB1 A2 IO81RSB1 IO80RSB1 A5 GEC0/IO77RSB1 GEB0/IO75RSB1 A8 IO73RSB1 A9 NC A10 VCC A11 IO71RSB1 A12 IO68RSB1 A13 IO63RSB1 A14 IO60RSB1 A15 NC A16 IO59RSB1 A17 IO57RSB1 ...

Page 134

Package Pin Assignments 132-Pin QFN Pin Number A3P030 Function C17 IO51RSB1 C18 NC C19 TCK C20 NC C21 VPUMP C22 VJTAG C23 NC C24 NC C25 NC C26 GDB0/IO38RSB0 C27 NC C28 VCCIB0 C29 IO32RSB0 C30 IO29RSB0 C31 IO28RSB0 C32 ...

Page 135

QFN Pin Number A3P060 Function A1 GAB2/IO00RSB1 A2 IO93RSB1 A3 VCCIB1 A4 GFC1/IO89RSB1 A5 GFB0/IO86RSB1 A6 VCCPLF A7 GFA1/IO84RSB1 A8 GFC2/IO81RSB1 A9 IO78RSB1 A10 VCC A11 GEB1/IO75RSB1 A12 GEA0/IO72RSB1 A13 GEC2/IO69RSB1 A14 IO65RSB1 A15 VCC A16 IO64RSB1 A17 IO63RSB1 ...

Page 136

Package Pin Assignments 132-Pin QFN Pin Number A3P060 Function C17 IO57RSB1 C18 NC C19 TCK C20 VMV1 C21 VPUMP C22 VJTAG C23 VCCIB0 C24 NC C25 NC C26 GCA1/IO42RSB0 C27 GCC0/IO39RSB0 C28 VCCIB0 C29 IO29RSB0 C30 GNDQ C31 GBA1/IO27RSB0 C32 ...

Page 137

QFN Pin Number A3P125 Function A1 GAB2/IO69RSB1 A2 IO130RSB1 A3 VCCIB1 A4 GFC1/IO126RSB1 A5 GFB0/IO123RSB1 A6 VCCPLF A7 GFA1/IO121RSB1 A8 GFC2/IO118RSB1 A9 IO115RSB1 A10 VCC A11 GEB1/IO110RSB1 A12 GEA0/IO107RSB1 A13 GEC2/IO104RSB1 A14 IO100RSB1 A15 VCC A16 IO99RSB1 A17 IO96RSB1 ...

Page 138

Package Pin Assignments 132-Pin QFN Pin Number A3P125 Function C17 IO83RSB1 C18 VCCIB1 C19 TCK C20 VMV1 C21 VPUMP C22 VJTAG C23 VCCIB0 C24 NC C25 NC C26 GCA1/IO55RSB0 C27 GCC0/IO52RSB0 C28 VCCIB0 C29 IO42RSB0 C30 GNDQ C31 GBA1/IO40RSB0 C32 ...

Page 139

... B18 IO78RSB2 B19 IO72RSB2 B20 GND B21 GNDQ B22 TMS B23 TDO B24 GDC0/IO58VDB1 ProASIC3 Flash Family FPGAs 132-Pin QFN Pin Number A3P250 Function B25 GND B26 IO54PDB1 B27 GCB2/IO52PDB1 B28 GND B29 GCB0/IO49NDB1 B30 GCC1/IO48PDB1 B31 GND B32 GBB2/IO42PDB1 B33 ...

Page 140

... Package Pin Assignments 132-Pin QFN Pin Number A3P250 Function C17 IO74RSB2 C18 VCCIB2 C19 TCK C20 VMV2 C21 VPUMP C22 VJTAG C23 VCCIB1 C24 IO53NSB1 C25 IO51NPB1 C26 GCA1/IO50PPB1 C27 GCC0/IO48NDB1 C28 VCCIB1 C29 IO42NDB1 C30 GNDQ C31 GBA1/IO40RSB0 C32 GBB0/IO37RSB0 ...

Page 141

... CSP 11 10 Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx ProASIC3 Flash Family FPGAs ...

Page 142

Package Pin Assignments 121-Pin CSP Pin Number A3P060 Function A1 GNDQ A2 IO01RSB0 A3 GAA1/IO03RSB0 A4 GAC1/IO07RSB0 A5 IO15RSB0 A6 IO13RSB0 A7 IO17RSB0 A8 GBB1/IO22RSB0 A9 GBA1/IO24RSB0 A10 GNDQ A11 VMV0 B1 GAA2/IO95RSB1 B2 IO00RSB0 B3 GAA0/IO02RSB0 B4 GAC0/IO06RSB0 B5 ...

Page 143

CSP Pin Number A3P060 Function K10 VPUMP K11 GDB1/IO47RSB0 L1 VMV1 L2 GNDQ L3 IO65RSB1 L4 IO63RSB1 L5 IO61RSB1 L6 IO58RSB1 L7 IO57RSB1 L8 IO55RSB1 L9 GNDQ L10 GDA0/IO50RSB0 L11 VMV1 ProASIC3 Flash Family FPGAs ...

Page 144

... Package Pin Assignments 100-Pin VQFP 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx visio n 9 ...

Page 145

VQFP Pin Number A3P030 Function 1 GND 2 IO82RSB1 3 IO81RSB1 4 IO80RSB1 5 IO79RSB1 6 IO78RSB1 7 IO77RSB1 8 IO76RSB1 9 GND 10 IO75RSB1 11 IO74RSB1 12 GEC0/IO73RSB1 13 GEA0/IO72RSB1 14 GEB0/IO71RSB1 15 IO70RSB1 16 IO69RSB1 17 VCC ...

Page 146

Package Pin Assignments 100-Pin VQFP Pin Number A3P060 Function 1 GND 2 GAA2/IO51RSB1 3 IO52RSB1 4 GAB2/IO53RSB1 5 IO95RSB1 6 GAC2/IO94RSB1 7 IO93RSB1 8 IO92RSB1 9 GND 10 GFB1/IO87RSB1 11 GFB0/IO86RSB1 12 VCOMPLF 13 GFA0/IO85RSB1 14 VCCPLF 15 GFA1/IO84RSB1 16 ...

Page 147

VQFP Pin Number A3P125 Function 1 GND 2 GAA2/IO67RSB1 3 IO68RSB1 4 GAB2/IO69RSB1 5 IO132RSB1 6 GAC2/IO131RSB1 7 IO130RSB1 8 IO129RSB1 9 GND 10 GFB1/IO124RSB1 11 GFB0/IO123RSB1 12 VCOMPLF 13 GFA0/IO122RSB1 14 VCCPLF 15 GFA1/IO121RSB1 16 GFA2/IO120RSB1 17 VCC ...

Page 148

... GDA1/IO60USB1 58 GDC0/IO58VDB1 59 GDC1/IO58UDB1 60 IO52NDB1 61 GCB2/IO52PDB1 62 GCA1/IO50PDB1 63 GCA0/IO50NDB1 64 GCC0/IO48NDB1 65 GCC1/IO48PDB1 66 VCCIB1 67 GND 68 VCC 69 IO43NDB1 70 GBC2/IO43PDB1 71 GBB2/IO42PSB1 72 IO41NDB1 R e visio n 9 100-Pin VQFP Pin Number A3P250 Function 73 GBA2/IO41PDB1 74 VMV1 75 GNDQ 76 GBA1/IO40RSB0 77 GBA0/IO39RSB0 78 GBB1/IO38RSB0 79 GBB0/IO37RSB0 80 GBC1/IO36RSB0 81 GBC0/IO35RSB0 82 IO29RSB0 83 IO27RSB0 84 IO25RSB0 85 IO23RSB0 86 IO21RSB0 87 VCCIB0 88 GND 89 ...

Page 149

... TQFP 144 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC3 Flash Family FPGAs 144-Pin TQFP ...

Page 150

Package Pin Assignments 144-Pin TQFP Pin Number A3P060 Function 1 GAA2/IO51RSB1 2 IO52RSB1 3 GAB2/IO53RSB1 4 IO95RSB1 5 GAC2/IO94RSB1 6 IO93RSB1 7 IO92RSB1 8 IO91RSB1 9 VCC 10 GND 11 VCCIB1 12 IO90RSB1 13 GFC1/IO89RSB1 14 GFC0/IO88RSB1 15 GFB1/IO87RSB1 16 ...

Page 151

TQFP Pin Number A3P060 Function 109 NC 110 NC 111 GBA1/IO24RSB0 112 GBA0/IO23RSB0 113 GBB1/IO22RSB0 114 GBB0/IO21RSB0 115 GBC1/IO20RSB0 116 GBC0/IO19RSB0 117 VCCIB0 118 GND 119 VCC 120 IO18RSB0 121 IO17RSB0 122 IO16RSB0 123 IO15RSB0 124 IO14RSB0 125 IO13RSB0 ...

Page 152

Package Pin Assignments 144-Pin TQFP Pin Number A3P125 Function 1 GAA2/IO67RSB1 2 IO68RSB1 3 GAB2/IO69RSB1 4 IO132RSB1 5 GAC2/IO131RSB1 6 IO130RSB1 7 IO129RSB1 8 IO128RSB1 9 VCC 10 GND 11 VCCIB1 12 IO127RSB1 13 GFC1/IO126RSB1 14 GFC0/IO125RSB1 15 GFB1/IO124RSB1 16 ...

Page 153

TQFP Pin Number A3P125 Function 109 GBA1/IO40RSB0 110 GBA0/IO39RSB0 111 GBB1/IO38RSB0 112 GBB0/IO37RSB0 113 GBC1/IO36RSB0 114 GBC0/IO35RSB0 115 IO34RSB0 116 IO33RSB0 117 VCCIB0 118 GND 119 VCC 120 IO29RSB0 121 IO28RSB0 122 IO27RSB0 123 IO25RSB0 124 IO23RSB0 125 IO21RSB0 ...

Page 154

... Package Pin Assignments 208-Pin PQFP 208 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx 208-Pin PQFP R e visio n 9 ...

Page 155

PQFP Pin Number A3P125 Function 1 GND 2 GAA2/IO67RSB1 3 IO68RSB1 4 GAB2/IO69RSB1 5 IO132RSB1 6 GAC2/IO131RSB1 IO130RSB1 10 IO129RSB1 IO128RSB1 VCC 17 GND ...

Page 156

Package Pin Assignments 208-Pin PQFP Pin Number A3P125 Function 109 TRST 110 VJTAG 111 GDA0/IO66RSB0 112 GDA1/IO65RSB0 113 GDB0/IO64RSB0 114 GDB1/IO63RSB0 115 GDC0/IO62RSB0 116 GDC1/IO61RSB0 117 NC 118 NC 119 NC 120 NC 121 NC 122 GND 123 VCCIB0 124 ...

Page 157

... IO94RSB2 59 IO93RSB2 60 IO92RSB2 61 IO91RSB2 62 VCCIB2 63 IO90RSB2 64 IO89RSB2 65 GND 66 IO88RSB2 67 IO87RSB2 68 IO86RSB2 69 IO85RSB2 70 IO84RSB2 71 VCC 72 VCCIB2 ProASIC3 Flash Family FPGAs 208-Pin PQFP Pin Number A3P250 Function 73 IO83RSB2 74 IO82RSB2 75 IO81RSB2 76 IO80RSB2 77 IO79RSB2 78 IO78RSB2 79 IO77RSB2 80 IO76RSB2 81 GND 82 IO75RSB2 83 IO74RSB2 84 IO73RSB2 85 IO72RSB2 86 IO71RSB2 87 IO70RSB2 88 VCC ...

Page 158

... IO28RSB0 174 IO27RSB0 175 IO26RSB0 176 IO25RSB0 177 IO24RSB0 178 GND 179 IO23RSB0 180 IO22RSB0 R e visio n 9 208-Pin PQFP Pin Number A3P250 Function 181 IO21RSB0 182 IO20RSB0 183 IO19RSB0 184 IO18RSB0 185 IO17RSB0 186 VCCIB0 187 VCC 188 IO16RSB0 189 ...

Page 159

PQFP Pin Number A3P400 Function 1 GND 2 GAA2/IO155UDB3 3 IO155VDB3 4 GAB2/IO154UDB3 5 IO154VDB3 6 GAC2/IO153UDB3 7 IO153VDB3 8 IO152UDB3 9 IO152VDB3 10 IO151UDB3 11 IO151VDB3 12 IO150PDB3 13 IO150NDB3 14 IO149PDB3 15 IO149NDB3 16 VCC 17 GND ...

Page 160

Package Pin Assignments 208-Pin PQFP Pin Number A3P400 Function 109 TRST 110 VJTAG 111 GDA0/IO79VDB1 112 GDA1/IO79UDB1 113 GDB0/IO78VDB1 114 GDB1/IO78UDB1 115 GDC0/IO77VDB1 116 GDC1/IO77UDB1 117 IO76VDB1 118 IO76UDB1 119 IO75NDB1 120 IO75PDB1 121 IO74RSB1 122 GND 123 VCCIB1 124 ...

Page 161

PQFP Pin Number A3P600 Function 1 GND 2 GAA2/IO174PDB3 3 IO174NDB3 4 GAB2/IO173PDB3 5 IO173NDB3 6 GAC2/IO172PDB3 7 IO172NDB3 8 IO171PDB3 9 IO171NDB3 10 IO170PDB3 11 IO170NDB3 12 IO169PDB3 13 IO169NDB3 14 IO168PDB3 15 IO168NDB3 16 VCC 17 GND ...

Page 162

Package Pin Assignments 208-Pin PQFP Pin Number A3P600 Function 109 TRST 110 VJTAG 111 GDA0/IO88NDB1 112 GDA1/IO88PDB1 113 GDB0/IO87NDB1 114 GDB1/IO87PDB1 115 GDC0/IO86NDB1 116 GDC1/IO86PDB1 117 IO84NDB1 118 IO84PDB1 119 IO82NDB1 120 IO82PDB1 121 IO81PSB1 122 GND 123 VCCIB1 124 ...

Page 163

PQFP Pin Number A3P1000 Function 1 GND 2 GAA2/IO225PDB3 3 IO225NDB3 4 GAB2/IO224PDB3 5 IO224NDB3 6 GAC2/IO223PDB3 7 IO223NDB3 8 IO222PDB3 9 IO222NDB3 10 IO220PDB3 11 IO220NDB3 12 IO218PDB3 13 IO218NDB3 14 IO216PDB3 15 IO216NDB3 16 VCC 17 GND ...

Page 164

Package Pin Assignments 208-Pin PQFP Pin Number A3P1000 Function 109 TRST 110 VJTAG 111 GDA0/IO113NDB1 112 GDA1/IO113PDB1 113 GDB0/IO112NDB1 114 GDB1/IO112PDB1 115 GDC0/IO111NDB1 116 GDC1/IO111PDB1 117 IO109NDB1 118 IO109PDB1 119 IO106NDB1 120 IO106PDB1 121 IO104PSB1 122 GND 123 VCCIB1 124 ...

Page 165

... FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ProASIC3 Flash Family FPGAs ...

Page 166

Package Pin Assignments 144-Pin FBGA Pin Number A3P060 Function A1 GNDQ A2 VMV0 A3 GAB0/IO04RSB0 A4 GAB1/IO05RSB0 A5 IO08RSB0 A6 GND A7 IO11RSB0 A8 VCC A9 IO16RSB0 A10 GBA0/IO23RSB0 A11 GBA1/IO24RSB0 A12 GNDQ B1 GAB2/IO53RSB1 B2 GND B3 GAA0/IO02RSB0 B4 ...

Page 167

FBGA Pin Number A3P060 Function K1 GEB0/IO74RSB1 K2 GEA1/IO73RSB1 K3 GEA0/IO72RSB1 K4 GEA2/IO71RSB1 K5 IO65RSB1 K6 IO64RSB1 K7 GND K8 IO57RSB1 K9 GDC2/IO56RSB1 K10 GND K11 GDA0/IO50RSB0 K12 GDB0/IO48RSB0 L1 GND L2 VMV1 L3 GEB2/IO70RSB1 L4 IO67RSB1 L5 VCCIB1 ...

Page 168

Package Pin Assignments 144-Pin FBGA Pin Number A3P125 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO11RSB0 A6 GND A7 IO18RSB0 A8 VCC A9 IO25RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO69RSB1 B2 GND B3 GAA0/IO00RSB0 B4 ...

Page 169

FBGA Pin Number A3P125 Function K1 GEB0/IO109RSB1 K2 GEA1/IO108RSB1 K3 GEA0/IO107RSB1 K4 GEA2/IO106RSB1 K5 IO100RSB1 K6 IO98RSB1 K7 GND K8 IO73RSB1 K9 GDC2/IO72RSB1 K10 GND K11 GDA0/IO66RSB0 K12 GDB0/IO64RSB0 L1 GND L2 VMV1 L3 GEB2/IO105RSB1 L4 IO102RSB1 L5 VCCIB1 ...

Page 170

... IO51NDB1 F1 GFB0/IO109NPB3 F2 VCOMPLF F3 GFB1/IO109PPB3 F4 IO107NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO48NDB1 F9 GCB0/IO49NPB1 F10 GND F11 GCA1/IO50PDB1 F12 GCA2/IO51PDB1 R e visio n 9 144-Pin FBGA Pin Number A3P250 Function G1 GFA1/IO108PPB3 G2 GND G3 VCCPLF G4 GFA0/IO108NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO58UPB1 G9 IO53NDB1 G10 GCC2/IO53PDB1 G11 IO52NDB1 G12 GCB2/IO52PDB1 H1 VCC H2 ...

Page 171

... FBGA Pin Number A3P250 Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 GEB2/IO96RSB2 L4 IO91RSB2 L5 VCCIB2 L6 IO82RSB2 L7 IO80RSB2 L8 IO72RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO95RSB2 M3 IO92RSB2 M4 IO89RSB2 M5 IO87RSB2 ...

Page 172

Package Pin Assignments 144-Pin FBGA Pin Number A3P400 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO30RSB0 A8 VCC A9 IO34RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO154UDB3 B2 GND B3 GAA0/IO00RSB0 B4 ...

Page 173

FBGA Pin Number A3P400 Function K1 GEB0/IO136NDB3 K2 GEA1/IO135PDB3 K3 GEA0/IO135NDB3 K4 GEA2/IO134RSB2 K5 IO127RSB2 K6 IO121RSB2 K7 GND K8 IO104RSB2 K9 GDC2/IO82RSB2 K10 GND K11 GDA0/IO79VDB1 K12 GDB0/IO78VDB1 L1 GND L2 VMV3 L3 GEB2/IO133RSB2 L4 IO128RSB2 L5 VCCIB2 ...

Page 174

Package Pin Assignments 144-Pin FBGA Pin Number A3P600 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO34RSB0 A8 VCC A9 IO50RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO173PDB3 B2 GND B3 GAA0/IO00RSB0 B4 ...

Page 175

FBGA Pin Number A3P600 Function K1 GEB0/IO145NDB3 K2 GEA1/IO144PDB3 K3 GEA0/IO144NDB3 K4 GEA2/IO143RSB2 K5 IO119RSB2 K6 IO111RSB2 K7 GND K8 IO94RSB2 K9 GDC2/IO91RSB2 K10 GND K11 GDA0/IO88NDB1 K12 GDB0/IO87NDB1 L1 GND L2 VMV3 L3 GEB2/IO142RSB2 L4 IO136RSB2 L5 VCCIB2 ...

Page 176

Package Pin Assignments 144-Pin FBGA Pin Number A3P1000 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO44RSB0 A8 VCC A9 IO69RSB0 A10 GBA0/IO76RSB0 A11 GBA1/IO77RSB0 A12 GNDQ B1 GAB2/IO224PDB3 B2 GND B3 GAA0/IO00RSB0 B4 ...

Page 177

FBGA Pin Number A3P1000 Function K1 GEB0/IO189NDB3 K2 GEA1/IO188PDB3 K3 GEA0/IO188NDB3 K4 GEA2/IO187RSB2 K5 IO169RSB2 K6 IO152RSB2 K7 GND K8 IO117RSB2 K9 GDC2/IO116RSB2 K10 GND K11 GDA0/IO113NDB1 K12 GDB0/IO112NDB1 L1 GND L2 VMV3 L3 GEB2/IO186RSB2 L4 IO172RSB2 L5 VCCIB2 ...

Page 178

... Package Pin Assignments 256-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner visio ...

Page 179

... D13 NC D14 GBB2/IO42PPB1 D15 NC D16 IO44NDB1 E1 IO113PDB3 IO116VDB3 E4 IO115UDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO19RSB0 ProASIC3 Flash Family FPGAs 256-Pin FBGA Pin Number A3P250 Function E9 IO24RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 E13 GBC2/IO43PDB1 E14 IO46RSB1 E15 NC E16 IO45PDB1 F1 IO113NDB3 F2 IO112PPB3 IO115VDB3 F5 VCCIB3 F6 ...

Page 180

... VCC L11 GND L12 VCCIB1 L13 GDB0/IO59VPB1 L14 IO57VDB1 L15 IO57UDB1 L16 IO56PDB1 M1 IO103PDB3 IO101NPB3 M4 GEC0/IO100NPB3 R e visio n 9 256-Pin FBGA Pin Number A3P250 Function M5 VMV3 M6 VCCIB2 M7 VCCIB2 IO74RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 NC M14 GDB1/IO59UPB1 M15 GDC1/IO58UDB1 M16 ...

Page 181

... R13 GDB2/IO62RSB2 R14 TDI R15 NC R16 TDO T1 GND T2 IO94RSB2 T3 GEB2/IO96RSB2 T4 IO93RSB2 T5 IO90RSB2 T6 IO87RSB2 T7 IO83RSB2 T8 IO79RSB2 T9 IO78RSB2 T10 IO73RSB2 T11 IO70RSB2 T12 GDC2/IO63RSB2 256-Pin FBGA Pin Number A3P250 Function T13 IO67RSB2 T14 GDA2/IO61RSB2 T15 TMS T16 GND ProASIC3 Flash Family FPGAs 3- 55 ...

Page 182

Package Pin Assignments 256-Pin FBGA Pin Number A3P400 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO17RSB0 A7 IO22RSB0 A8 IO28RSB0 A9 IO34RSB0 A10 IO37RSB0 A11 IO41RSB0 A12 IO43RSB0 A13 GBB1/IO57RSB0 A14 GBA0/IO58RSB0 A15 GBA1/IO59RSB0 A16 ...

Page 183

FBGA Pin Number A3P400 Function G13 GCC1/IO67PPB1 G14 IO64NPB1 G15 IO73PDB1 G16 IO73NDB1 H1 GFB0/IO146NPB3 H2 GFA0/IO145NDB3 H3 GFB1/IO146PPB3 H4 VCOMPLF H5 GFC0/IO147NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO67NPB1 H13 GCB1/IO68PPB1 ...

Page 184

Package Pin Assignments 256-Pin FBGA Pin Number A3P400 Function P9 IO98RSB2 P10 IO95RSB2 P11 IO88RSB2 P12 IO84RSB2 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO79VDB1 R1 GEA1/IO135PDB3 R2 GEA0/IO135NDB3 R3 IO127RSB2 R4 GEC2/IO132RSB2 R5 IO123RSB2 R6 IO118RSB2 R7 IO112RSB2 R8 ...

Page 185

FBGA Pin Number A3P600 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO11RSB0 A6 IO16RSB0 A7 IO18RSB0 A8 IO28RSB0 A9 IO34RSB0 A10 IO37RSB0 A11 IO41RSB0 A12 IO43RSB0 A13 GBB1/IO57RSB0 A14 GBA0/IO58RSB0 A15 GBA1/IO59RSB0 A16 GND B1 GAB2/IO173PDB3 ...

Page 186

Package Pin Assignments 256-Pin FBGA Pin Number A3P600 Function G13 GCC1/IO69PPB1 G14 IO65NPB1 G15 IO75PDB1 G16 IO75NDB1 H1 GFB0/IO163NPB3 H2 GFA0/IO162NDB3 H3 GFB1/IO163PPB3 H4 VCOMPLF H5 GFC0/IO164NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 ...

Page 187

FBGA Pin Number A3P600 Function P9 IO107RSB2 P10 IO104RSB2 P11 IO97RSB2 P12 VMV1 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO88NDB1 R1 GEA1/IO144PDB3 R2 GEA0/IO144NDB3 R3 IO139RSB2 R4 GEC2/IO141RSB2 R5 IO132RSB2 R6 IO127RSB2 R7 IO121RSB2 R8 IO114RSB2 R9 IO109RSB2 ...

Page 188

Package Pin Assignments 256-Pin FBGA Pin Number A3P1000 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO22RSB0 A7 IO28RSB0 A8 IO35RSB0 A9 IO45RSB0 A10 IO50RSB0 A11 IO55RSB0 A12 IO61RSB0 A13 GBB1/IO75RSB0 A14 GBA0/IO76RSB0 A15 GBA1/IO77RSB0 A16 ...

Page 189

FBGA Pin Number A3P1000 Function H3 GFB1/IO208PPB3 H4 VCOMPLF H5 GFC0/IO209NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO91NPB1 H13 GCB1/IO92PPB1 H14 GCA0/IO93NPB1 H15 IO96NPB1 H16 GCB0/IO92NPB1 J1 GFA2/IO206PSB3 J2 GFA1/IO207PDB3 J3 VCCPLF ...

Page 190

Package Pin Assignments 256-Pin FBGA Pin Number A3P1000 Function R5 IO168RSB2 R6 IO163RSB2 R7 IO157RSB2 R8 IO149RSB2 R9 IO143RSB2 R10 IO138RSB2 R11 IO131RSB2 R12 IO125RSB2 R13 GDB2/IO115RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO183RSB2 T3 GEB2/IO186RSB2 T4 ...

Page 191

... FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ProASIC3 Flash Family FPGAs ...

Page 192

Package Pin Assignments 484-Pin FBGA Pin Number A3P400 Function A1 GND A2 GND A3 VCCIB0 IO15RSB0 A7 IO18RSB0 A10 IO23RSB0 A11 IO29RSB0 A12 IO35RSB0 A13 IO36RSB0 A14 NC A15 NC A16 ...

Page 193

FBGA Pin Number A3P400 Function E21 NC E22 IO154VDB3 F5 IO155VDB3 F6 IO11RSB0 F7 IO07RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO20RSB0 F11 IO24RSB0 F12 IO33RSB0 F13 IO39RSB0 F14 IO45RSB0 F15 GBC0/IO54RSB0 ...

Page 194

Package Pin Assignments 484-Pin FBGA Pin Number A3P400 Function K19 IO73NDB1 K20 NC K21 NC K22 GFB0/IO146NPB3 L5 GFA0/IO145NDB3 L6 GFB1/IO146PPB3 L7 VCOMPLF L8 GFC0/IO147NPB3 L9 VCC L10 GND L11 GND L12 ...

Page 195

FBGA Pin Number A3P400 Function R17 GDB1/IO78UPB1 R18 GDC1/IO77UDB1 R19 IO75NDB1 R20 VCC R21 NC R22 IO140NDB3 T5 IO138PPB3 T6 GEC1/IO137PPB3 T7 IO131RSB2 T8 GNDQ T9 GEA2/IO134RSB2 T10 IO117RSB2 T11 IO111RSB2 ...

Page 196

Package Pin Assignments 484-Pin FBGA Pin Number A3P400 Function Y15 VCC Y16 NC Y17 NC Y18 GND Y19 NC Y20 NC Y21 NC Y22 VCCIB1 AA1 GND AA2 VCCIB3 AA3 NC AA4 NC AA5 NC AA6 NC AA7 NC AA8 ...

Page 197

FBGA Pin Number A3P600 Function A1 GND A2 GND A3 VCCIB0 IO09RSB0 A7 IO15RSB0 A10 IO22RSB0 A11 IO23RSB0 A12 IO29RSB0 A13 IO35RSB0 A14 NC A15 NC A16 IO46RSB0 A17 IO48RSB0 ...

Page 198

Package Pin Assignments 484-Pin FBGA Pin Number A3P600 Function E21 NC E22 IO173NDB3 F5 IO174NDB3 F6 VMV3 F7 IO07RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO20RSB0 F11 IO24RSB0 F12 IO33RSB0 F13 IO39RSB0 F14 ...

Page 199

FBGA Pin Number A3P600 Function K19 IO75NDB1 K20 NC K21 IO76NDB1 K22 IO76PDB1 IO155PDB3 GFB0/IO163NPB3 L5 GFA0/IO162NDB3 L6 GFB1/IO163PPB3 L7 VCOMPLF L8 GFC0/IO164NPB3 L9 VCC L10 GND L11 GND L12 GND L13 GND ...

Page 200

Package Pin Assignments 484-Pin FBGA Pin Number A3P600 Function R17 GDB1/IO87PPB1 R18 GDC1/IO86PDB1 R19 IO84NDB1 R20 VCC R21 IO81NDB1 R22 IO82PDB1 T1 IO152PDB3 T2 IO152NDB3 IO150NDB3 T5 IO147PPB3 T6 GEC1/IO146PPB3 T7 IO140RSB2 T8 GNDQ T9 GEA2/IO143RSB2 T10 ...

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