A3P250-VQG100 Actel, A3P250-VQG100 Datasheet - Page 90

• Manufacturer Part Number: A3P250-VQG100
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of A3P250-VQG100

• Processor Series: A3P250
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 157
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3 DC and Switching Characteristics
Figure 2-17 • Output Register Timing Diagram
Table 2-99 • Output Data Register Propagation Delays
2- 76
Enable
Preset
DOUT
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLK
Data_out
Clear
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Output Register
Timing Characteristics
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
50%
50%
t
1
OSUE
t
OHE
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
Description
J
50%
50%
= 70°C, Worst-Case VCC = 1.425 V
50%
t
OWPRE
t
OPRE2Q
50%
50%
R e visio n 9
t
ORECPRE
t
50%
OCLR2Q
50%
t
OWCLR
50%
50%
50%
Table 2-6 on page 2-6
t
ORECCLR
50%
t
OCKMPWH
0.59 0.67 0.79
0.31 0.36 0.42
0.00 0.00 0.00
0.44 0.50 0.59
0.00 0.00 0.00
0.80 0.91 1.07
0.80 0.91 1.07
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
–2
t
50%
OREMPRE
for derating values.
t
50%
OCKMPWL
–1
Std. Units
t
OREMCLR
50%
50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns