LFXP20C-3FN256C Lattice, LFXP20C-3FN256C Datasheet - Page 196
![FPGA - Field Programmable Gate Array 19.7K LUTS 188 I/O](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP20C-3FN256C
Manufacturer Part Number
LFXP20C-3FN256C
Description
FPGA - Field Programmable Gate Array 19.7K LUTS 188 I/O
Manufacturer
Lattice
Specifications of LFXP20C-3FN256C
Number Of Programmable I/os
188
Data Ram Size
405504
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP20C-3FN256C
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LFXP20C-3FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 9-33. FIFO Without Output Registers, Start of Data Write Cycle
The WrEn signal has to be high to start writing into the FIFO. The Empty and Almost Empty flags are high to begin
and Full and Almost full are low.
When the first data gets written into the FIFO, the Empty flag de-asserts (or goes low), as the FIFO is no longer
empty. In this figure we are assuming that the Almost Empty setting flag setting is 3 (address location 3). So the
Almost Empty flag gets de-asserted when the 3rd address location gets filled.
Now let is assume that we continue to write into the FIFO to fill it. When the FIFO is filled, the Almost Full and Full
Flags are asserted. Figure 9-34 shows the behavior of these flags. In this figure we assume that FIFO depth is ‘N’.
Almost
Almost
Empty
Empty
Reset
Clock
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
9-31
Invalid Q
Data_3
LatticeECP/EC and LatticeXP Devices
Data_4
Data_5
Memory Usage Guide
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