LFXP20C-3FN256C Lattice, LFXP20C-3FN256C Datasheet - Page 276
![FPGA - Field Programmable Gate Array 19.7K LUTS 188 I/O](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP20C-3FN256C
Manufacturer Part Number
LFXP20C-3FN256C
Description
FPGA - Field Programmable Gate Array 19.7K LUTS 188 I/O
Manufacturer
Lattice
Specifications of LFXP20C-3FN256C
Number Of Programmable I/os
188
Data Ram Size
405504
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
Company:
Part Number:
LFXP20C-3FN256C
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LFXP20C-3FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Appendix A. Clock Preferences
A few key clock preferences are introduced below. Refer to the ‘Help’ file for other preferences and detailed infor-
mation.
ASIC
The following preference command assigns a phase of 90° to the CIMDLLA CLKOP.
FREQUENCY
The following physical preference command assigns a frequency of 100 MHz to a net named clk1.
The following preference specifies a hold margin value for each clock domain.
MAXSKEW
The following command assigns a maximum skew of 5 ns to a net named NetB.
MULTICYCLE
The following command will relax the period to 50 ns for the path starting at COMPA to COMPB (NET1).
PERIOD
The following command assigns a clock period of 30 ns to the port named Clk1.
PROHIBIT
This command prohibits the use of a primary clock to route a clock net named bf_clk.
CLOCK_TO_OUT
Specifies a maximum allowable output delay relative to a clock.
Below are two preferences using both the CLKPORT and CLKNET keywords showing the corresponding scope of
TRACE reporting.
The CLKNET will stop tracing the path before the PLL, so you will not get PLL compensation timing numbers.
The above preference will yield the following clock path:
ASIC "my_pll" TYPE "EXHXPLLB" CLKOS_PHASE=90;
FREQUENCY NET "clk1" 100 MHz;
FREQUENCY NET "RX_CLKA_CMOS_c" 100.000 MHz HOLD_MARGIN 1 ns;
MAXSKEW NET "NetB" 5 NS;
MULTICYCLE "PATH1" START COMP "COMPA" END COMP "COMPB" NET "NET1" 50 NS ;
PERIOD PORT "Clk1" 30 NS;
PROHIBIT PRIMARY NET "bf_clk";
CLOCK_TO_OUT PORT "RxAddr_0" 6.000000 ns CLKNET "pll_rxclk" ;
11-20
sysCLOCK PLL Design and Usage Guide
LatticeECP/EC and LatticeXP
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