LFXP20C-3FN256C Lattice, LFXP20C-3FN256C Datasheet - Page 313
![FPGA - Field Programmable Gate Array 19.7K LUTS 188 I/O](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP20C-3FN256C
Manufacturer Part Number
LFXP20C-3FN256C
Description
FPGA - Field Programmable Gate Array 19.7K LUTS 188 I/O
Manufacturer
Lattice
Specifications of LFXP20C-3FN256C
Number Of Programmable I/os
188
Data Ram Size
405504
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 13-6 shows an asynchronous peripheral write sequence using the Bypass option. To send configuration
data to a device, the WRITEN signal has to be asserted. During the write cycle, the BUSY signal provides hand-
shaking between the host system and the LatticeXP device. When BUSY is low the device is ready to read a byte
of data at the next rising edge of CCLK. The BUSY signal is set high when the device reads the data and the device
requires extra clock cycles to process the data.
Self Download Mode
Self Download Mode (SDM) allows the FPGA to configure itself without using any external devices, and because
the bitstream is not exposed this is also a very secure configuration mode. The user may access on-chip Flash
using ispJTAG or the slave parallel port on the sysCONFIG pins.
JTAG may access the on-chip Flash any time the device is powered up, without disturbing device operation. JTAG
may also read and write the configuration SRAM. If access to the on-chip Flash and SRAM is limited to JTAG then
CONFIG_MODE should be set to None, freeing the dual-purpose pins for use as general purpose I/O.
The slave parallel port can also be used to access on-chip Flash. If the slave parallel port is used then
CONFIG_MODE should be set to Slave_Parallel. WRITEN, CSN, and CS1N must be held low to write to on-chip
Flash; data is input from D[0:7]. The slave parallel port can also be used for readback of both Flash and SRAM. By
driving the WRITEN pin low, and CSN and CS1N low, the device will input the readback instructions on the D[0:7]
pins; a bit in the read command will determine if the read is directed to Flash or SRAM. In order to support read-
back while the device is in user mode (the DONE pin is high) the PERSISTENT bit in ispLEVER’s Preference Editor
must be set to ON.
SDM does not support overflow.
ispJTAG Mode
The LatticeXP device can be configured through the ispJTAG port. The ispJTAG port is always on and available,
regardless of the configuration mode selected. A CONFIG_MODE of None can be selected in the Lattice isp-
LEVER design software to tell the place and route tools that the JTAG port will be used exclusively, i.e. the serial
and parallel ports will not be used. Setting the CONFIG_MODE to None allows software to use all of the dual-pur-
pose pins as general purpose I/Os.
ISC 1532
Configuration through the ispJTAG port conforms to the IEEE 1532 Standard. The Boundary Scan cells take con-
trol of the I/Os during any 1532 mode instruction. The Boundary Scan cells can be set to a pre-determined value
whenever using the JTAG 1532 mode. Because of this the dedicated pins, such as DONE, cannot be relied upon
for valid configuration status.
ispJTAG (1149.1 interface)
Self Download Mode (SDM)
Configuration Mode
Configuration Mode
CFG[1]
CFG[1]
1
X
13-14
CFG[0]
CFG[0]
X
1
LatticeXP sysCONFIG Usage Guide
None/Slave_Parallel
CONFIG_MODE
CONFIG_MODE
None
Chain Mode
Chain Mode
Disable
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