AGL125V2-FGG144 Actel, AGL125V2-FGG144 Datasheet - Page 140
![FPGA - Field Programmable Gate Array 125K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL125V2-FGG144
Manufacturer Part Number
AGL125V2-FGG144
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL125V2-FGG144
Processor Series
AGL125
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
125 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL125V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
ON
Quantity:
20 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL125V2-FGG144I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
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IGLOO DC and Switching Characteristics
Table 2-192 • RAM4K9
2- 12 6
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
C2CWWL
C2CRWH
C2CWRH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
1.2 V DC Core Voltage
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (flow-through, WMODE = 1)
Clock High to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable write after write on same address -
Applicable to Closing Edge
Address collision clk-to-clk delay for reliable read access after write on same address -
Applicable to Opening Edge
Address collision clk-to-clk delay for reliable write access after read on same address -
Applicable to Opening Edge
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum frequency
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.14 V
Description
R ev isio n 1 8
Table 2-7 on page 2-7
for derating values.
10.90
1.53
0.29
1.50
0.29
3.05
0.29
1.33
0.66
6.61
5.72
3.38
0.30
0.89
1.01
3.86
3.86
1.12
5.93
1.18
Std.
92
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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