AGL125V2-FGG144 Actel, AGL125V2-FGG144 Datasheet - Page 29
![FPGA - Field Programmable Gate Array 125K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL125V2-FGG144
Manufacturer Part Number
AGL125V2-FGG144
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL125V2-FGG144
Processor Series
AGL125
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
125 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL125V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
ON
Quantity:
20 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL125V2-FGG144I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
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Table 2-20 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices
Parameter
PAC1
PAC2
PAC3
PAC4
PAC5
PAC6
PAC7
PAC8
PAC9
PAC10
PAC11
PAC12
PAC13
*
For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet
calculator or SmartPower tool in Libero IDE.
Clock contribution of a
Global Rib
Clock contribution of a
Global Spine
Clock contribution of a
VersaTile row
Clock contribution of a
VersaTile
sequential module
First contribution of a
VersaTile
sequential module
Second contribution of a
VersaTile
sequential module
Contribution
VersaTile
combinatorial module
Average contribution of a
routing net
Contribution of an I/O
input
dependent)
Contribution of an I/O
output
dependent)
Average contribution of a
RAM block during a read
operation
Average contribution of a
RAM block during a write
operation
Dynamic PLL contribution
For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage
Definition
pin
pin
used
used
used
used
(standard-
(standard-
of
as
as
as
as
a
a
a
a
a
AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015
9.28
1.59
See
See
Table 2-12 on page 2-10
Table 2-15 on page 2-11
8.19
1.19
R ev i si o n 1 8
Device Specific Dynamic Power
8.19
1.01
7.07
1.01
(µW/MHz)
0.045
0.186
25.00
30.00
0.52
0.07
0.45
2.10
0.11
through
through
7.07
0.52
Table 2-17 on page
Table 2-14 on page
IGLOO Low Power Flash FPGAs
5.96
0.52
5.96
0.26
2-12.
2-11.
5.96
0.26
2- 15
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