AGL125V2-FGG144 Actel, AGL125V2-FGG144 Datasheet - Page 232
![FPGA - Field Programmable Gate Array 125K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL125V2-FGG144
Manufacturer Part Number
AGL125V2-FGG144
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL125V2-FGG144
Processor Series
AGL125
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
125 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL125V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
ON
Quantity:
20 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL125V2-FGG144I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
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Datasheet Information
4- 6
Revision
Advance v0.7
(continued)
The
This document was previously in datasheet Advance v0.7. As a result of moving
to the handbook format, Actel has restarted the version numbers. The new
version number is Advance v0.1.
Table 2-4 • IGLOO CCC/PLL Specification and Table 2-5 • IGLOO CCC/PLL
Specification were updated.
The former Table 2-16 • Maximum I/O Frequency for Single-Ended and
Differential I/Os in All Banks in IGLOO Devices (maximum drive strength and
high slew selected) was removed.
The "During Flash*Freeze Mode" section was updated to include information
about the output of the I/O to the FPGA core
Table 2-31 • Flash*Freeze Pin Location in IGLOO Family Packages (device-
independent) was updated to add UC81 and CS281. Flash*Freeze pins were
assigned for CS81, CS121, and CS196.
Figure 2-40 • Flash*Freeze Mode Type 2 – Timing Diagram was updated to
modify the LSICC Signal.
Information regarding calculation of the quiescent supply current was added to
the "Quiescent Supply Current" section.
Table
Flash*Freeze Mode
Table 3-9 • Quiescent Supply Current (I
(VCC = 0 V)
Table 3-11 • Quiescent Supply Current (I
was updated.
Table 3-115 • Minimum and Maximum DC Input and Output Levels was
updated.
The "121-Pin CSP" and "281-Pin CSP" packages are new.
The "81-Pin CSP" table for the AGL030 device was updated to change the G6
pin function to IO44RSB1 and the JG pin function to IO45RSB1.
The "121-Pin CSP" table for the AGL060 device is new.
The "256-Pin FBGA" table for the AGL1000 device is new.
The "281-Pin CSP" table for the AGL 600 device is new.
The "100-Pin VQFP" table for the AGL060 device is new.
The "144-Pin FBGA" table for the AGL250 device is new.
The "144-Pin FBGA" table for the AGL1000 device is new.
The "484-Pin FBGA" table for the AGL600 device is new.
The "484-Pin FBGA" table for the AGL1000 device is new.
Table 3-156 • JTAG 1532 was updated and Table 3-155 • JTAG 1532 is new.
"1.2 V LVCMOS (JESD8-12A)" section
3-8 • Quiescent
†
was updated.
†
was updated.
Supply
R ev isio n 1 8
Changes
Current
DD
DD
) Characteristics, IGLOO Sleep Mode
is new.
.
), No IGLOO Flash*Freeze Mode1
(I
DD
)
Characteristics,
IGLOO
4-5, 4-7
3-104
Page
2-19,
4-24
4-38
2-74
2-20
2-57
2-61
2-55
3-58
4-34
4-18
4-28
4-43
N/A
N/A
3-6
3-6
3-6
3-7
4-4
4-6
4-8
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