AGL125V2-FGG144 Actel, AGL125V2-FGG144 Datasheet - Page 71
![FPGA - Field Programmable Gate Array 125K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL125V2-FGG144
Manufacturer Part Number
AGL125V2-FGG144
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL125V2-FGG144
Processor Series
AGL125
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
125 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL125V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
ON
Quantity:
20 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL125V2-FGG144I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
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Table 2-80 • Minimum and Maximum DC Input and Output Levels
Figure 2-8 • AC Loading
Table 2-81 • AC Waveforms, Measuring Points, and Capacitive Loads
2.5 V
LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Notes:
1. I
2. I
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
*
Measuring point = Vtrip. See
larger when operating outside recommended ranges
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Min.
–0.3
–0.3
–0.3
–0.3
Applicable to Standard I/O Banks
V
Test Point
Datapath
VIL
Max.
0.7
0.7
0.7
0.7
V
Table 2-28 on page 2-28
Min.
1.7
1.7
1.7
1.7
V
5 pF
Input High (V)
VIH
Max.
2.5
3.6
3.6
3.6
3.6
V
Enable Path
Test Point
Max.
VOL
0.7
0.7
0.7
0.7
R = 1 k
V
for a complete table of trip points.
R ev i si o n 1 8
VOH
Min.
Measuring Point* (V)
1.7
1.7
1.7
1.7
V
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
mA mA
I
OL
2
6
4
8
1.2
I
OH
2
6
4
8
HZ
ZH
/ t
HZ
LZ
/ t
LZ
Max.
mA
I
ZHS
OSH
16
16
32
32
/ t
/ t
ZL
ZH
3
/ t
IGLOO Low Power Flash FPGAs
/ t
/ t
ZL
ZLS
ZHS
/ t
ZLS
Max.
mA
I
C
OSL
18
18
37
37
LOAD
3
5
(pF)
µA
I
10
10
IL
10
10
1
4
µA
I
10
10
IH
10
10
2- 57
2
4
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