MMA8452QR1 Freescale Semiconductor, MMA8452QR1 Datasheet - Page 4

• Manufacturer Part Number: MMA8452QR1
• Description: Board Mount Accelerometers LOW G 3-AXIS 12BT EX VLT
• Manufacturer: Freescale Semiconductor

Specifications of MMA8452QR1

• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 4 g, 8 g
• Digital Output - Number Of Bits: 8 bit, 12 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.95 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Digital Output - Bus Interface: I2C
• Shutdown: Yes
• Sensitivity: 256 count/g, 512 count/g, 1024 count/g
• Package / Case: QFN-16
• Output Type: Digital
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Acceleration Range: ± 2g, ± 4g, ± 8g
• No. Of Axes: 3
• Ic Interface Type: I2C
• Sensor Case Style: QFN
• No. Of Pins: 16
• Supply Voltage Range: 1.95V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4
MMA8452Q
6.4
6.5
6.6
6.7
0x18 FF_MT_COUNT Debounce Register ................................................................................................................. 32
0x1D: Transient_CFG Register ................................................................................................................................... 34
0x1E TRANSIENT_SRC Register ............................................................................................................................... 34
0x1F TRANSIENT_THS Register ................................................................................................................................ 35
0x20 TRANSIENT_COUNT ......................................................................................................................................... 35
0x21: PULSE_CFG Pulse Configuration Register ....................................................................................................... 36
0x22: PULSE_SRC Pulse Source Register ................................................................................................................. 36
0x23 - 0x25: PULSE_THSX, Y, Z Pulse Threshold for X, Y & Z Registers ................................................................. 37
0x26: PULSE_TMLT Pulse Time Window 1 Register .................................................................................................. 37
0x27: PULSE_LTCY Pulse Latency Timer Register .................................................................................................... 38
0x28 PULSE_WIND Register (Read/Write) ................................................................................................................. 39
0x2A: CTRL_REG1 System Control 1 Register .......................................................................................................... 41
Table 29. FF_MT_COUNT Description ..................................................................................................................... 32
Table 30. FF_MT_COUNT Relationship with the ODR ............................................................................................ 32
Figure 14. DBCNTM Bit Function ............................................................................................................................. 33
Transient (HPF) Acceleration Detection ................................................................................................................... 34
Table 31. TRANSIENT_CFG Description ................................................................................................................. 34
Table 32. TRANSIENT_SRC Description ................................................................................................................. 34
Table 33. TRANSIENT_THS Description ................................................................................................................. 35
Table 34. TRANSIENT_COUNT Description ............................................................................................................ 35
Table 35. TRANSIENT_COUNT Relationship with the ODR .................................................................................... 35
Single, Double and Directional Tap Detection Registers .......................................................................................... 36
Table 36. PULSE_CFG Description .......................................................................................................................... 36
Table 37. PULSE_SRC Description .......................................................................................................................... 36
Table 38. PULSE_THSX Description ........................................................................................................................ 37
Table 39. PULSE_THSY Description ........................................................................................................................ 37
Table 40. PULSE_THSZ Description ........................................................................................................................ 37
Table 41. PULSE_TMLT Description ........................................................................................................................ 37
Table 42. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 1 ........................................................... 37
Table 43. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 0 ........................................................... 38
Table 44. PULSE_LTCY Description ........................................................................................................................ 38
Table 45. Time Step for PULSE Latency @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 1 ..................... 38
Table 46. Time Step for PULSE Latency @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0 ..................... 38
Table 47. PULSE_WIND Description ........................................................................................................................ 39
Table 48. Time Step for PULSE Detection Window @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 1 ..... 39
Table 49. Time Step for PULSE Detection Window @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0 ..... 39
Auto-WAKE/SLEEP Detection .................................................................................................................................. 40
Table 50. ASLP_COUNT Description ....................................................................................................................... 40
Table 51. ASLP_COUNT Relationship with ODR ..................................................................................................... 40
Table 52. SLEEP/WAKE Mode Gates and Triggers ................................................................................................. 40
Control Registers ...................................................................................................................................................... 41
Table 53. CTRL_REG1 Description .......................................................................................................................... 41
Table 54. SLEEP Mode Rate Description ................................................................................................................. 41
Table 55. System Output Data Rate Selection ......................................................................................................... 41
Table 56. Full Scale Selection .................................................................................................................................. 41
0x18 FF_MT_COUNT_Register (Read/Write) .................................................................................................... 32
0x1D TRANSIENT_CFG Register (Read/Write) ................................................................................................. 34
0x1E TRANSIENT_SRC Register (Read Only) ................................................................................................... 34
0x1F TRANSIENT_THS Register (Read/Write) .................................................................................................. 35
0x20 TRANSIENT_COUNT Register (Read/Write) ............................................................................................ 35
0x21 PULSE_CFG Register (Read/Write) .......................................................................................................... 36
0x22 PULSE_SRC Register (Read Only) ........................................................................................................... 36
0x23 PULSE_THSX Register (Read/Write) ........................................................................................................ 37
0x24 PULSE_THSY Register (Read/Write) ........................................................................................................ 37
0x25 PULSE_THSZ Register (Read/Write) ........................................................................................................ 37
0x26 PULSE_TMLT Register (Read/Write) ........................................................................................................ 37
0x27 PULSE_LTCY Register (Read/Write) ......................................................................................................... 38
0x29 ASLP_COUNT Register (Read/Write) ........................................................................................................ 40
0x2A CTRL_REG1 Register (Read/Write) .......................................................................................................... 41
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